CAT15002 Datasheet, PDF (7/15 Pages) Catalyst Semiconductor – Voltage Supervisor with 2-Kb and 4-Kb SPI Serial CMOS EEPROM

CAT15002, CAT15004
STATUS REGISTER
The Status Register, as shown in Table 2, contains a
number of status and control bits.
The ¯R¯D¯Y¯ (Ready) bit indicates whether the device is
busy with a write operation. This bit is automatically
set to 1 during an internal write cycle, and reset to 0
when the device is ready to accept commands. For
the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is
in a Write Enable state and when set to 0, the device
is in a Write Disable state.
The BP0 and BP1 (Block Protect) bits determine
which blocks are currently write protected. They are
set by the user with the WRSR command and are
non-volatile. The user is allowed to protect a quarter,
one half or the entire memory, by setting these bits
according to Table 3. The protected blocks then
become read-only.
Table 2. Status Register
7
6
5
1
1
1
4
3
2
1
0
1
BP1
BP0
WEL
¯R¯D¯Y¯
Table 3. Block Protection Bits
Status Register Bits
BP1
BP0 ^{Array Address Protected}
0
0
None
15002: C0-FF
0
1
15004: 180-1FF
15002: 80-FF
1
0
15004: 100-1FF
15002: 00-FF
1
1
15004: 000-1FF
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
© 2007 Catalyst Semiconductor, Inc.
7
Characteristics subject to change without notice
Doc. No. 1126 Rev. A