CAT523_04 Datasheet, PDF (6/11 Pages) Catalyst Semiconductor – Configured Digitally Programmable Potentiometer

CAT523
V_REF
V_REF, the voltage applied between pins V_REFH andV_REFL,
sets the DPP’s Zero to Full Scale output range where
V_REFL = Zero and V_REFH = Full Scale. V_REF can span the
full power supply range or just a fraction of it. In typical
applications V_REFH andV_REFL are connected across the
power supply rails. When using less than the full supply
voltage V_REFH is restricted to voltages between V_DD and
V_DD/2 and V_REFL to voltages between GND and V_DD/2.
READY/BUSY
When saving data to non-volatile memory, the Ready/
Busy output (RDY/BSY) signals the start and duration of
the non-volatile erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle
is complete. During this time the CAT523 will ignore any
data appearing at DI and no data will be output on DO.
RDY/BSY is internally ANDed with a low voltage detector
circuit monitoring V_DD. If V_DD is below the minimum value
required for non-volatile programming, RDY/BSY will
remain high following the program command indicating
a failure to record the desired data in non-volatile memory.
DATA OUTPUT
Data is output serially by the CAT523, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 523s to share a
single serial data line and simplifies interfacing multiple
523s to a microprocessor.
WRITING TO MEMORY
Programming the CAT523’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits are
clocked into the DPP control register via the DI pin. Data
enters on the clock’s rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is achieved by bringing PROG high for a
minimum of 3 ms. PROG must be brought high some-
time after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running through-
out the programming cycle. Internal control circuitry
takes care of ramping the programming voltage for data
transfer to the non-volatile memory cells. The CAT523’s
non-volatile memory cells will endure over 100,000 write
cycles and will retain data for a minimum of 100 years
without being refreshed.
READING DATA
Each time data is transferred into a DPP wiper control
register currently held data is shifted out via the D0 pin,
thus in every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP’s output. This feature allows µPs to
poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13^th clock cycle completes. In
doing so the non-volatile memory setting is reloaded into
the DPP wiper control register.
Figure 1. Writing to Memory
NEW DPP DATA
CURRENT DPP DATA
RDY/BSY
DPP
OUTPUT
DPP VALUE
DPP VALUE
DPP VALUE
Figure 2. Reading from Memory
to 1 2 3 4 5 6 7 8 9 10 11 12
CS
DI
1 A0 A1
CURRENT DPP DATA
DO
D0 D1 D2 D3 D4 D5 D6 D7
PROG
DPP
OUTPUT
CURRENT
DPP VALUE
NON-VOLATILE
Doc. No. 2005, Rev. E
6