CAT504 Datasheet, PDF (6/12 Pages) Catalyst Semiconductor – 8-Bit Quad DACpot

CAT504
V_REF
VREF, the voltage applied between pins VREFH andVREFL,
sets the DAC’s Zero to Full Scale output range where
VREFL = Zero and VREFH = Full Scale. VREF can span the
full power supply range or just a fraction of it. In typical
applications VREFH andVREFL are connected across the
power supply rails. When using less than the full supply
voltage VREFH is restricted to voltages between VDD and
VDD/2 and VREFL to voltages between GND and VDD/2.
V_PP
When saving data to non-volatile EEPROM memory an
external voltage of 18–20 volts must be applied to the
VPP pin. This voltage need only be present during the
programming cycle and may be removed or turned off
the remainder of the time. While it is not necessary to
remove or power down VPP between programming
cycles, some power sensitive applications may choose
to do so. In such cases, the VPP supply must be given
sufficient time to come up and stabilize before issuing
the PROG command.
DATA OUTPUT
Data is output serially by the CAT504, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 504s to share a
single serial data line and simplifies interfacing multiple
504s to a microprocessor.
WRITING TO MEMORY
Programming the CAT504’s EEPROM memory is ac-
complished through the application of an externally
generated programming voltage, VPP, and the control
signals: Chip Select (CS) and Program (PROG). With
CS high, a start bit followed by a two bit DAC address
and eight data bits are clocked into the DAC control
register via the DI pin. Data enters on the clock’s rising
edge. The DAC output changes to its new setting on the
clock cycle following D7, the last data bit.
Programming is achieved by bringing PROG high for a
minimum of 3 ms while supplying 18 to 20 volts to the V_PP
pin. PROG must be brought high sometime after the
start bit and at least 150 ns prior to the rising edge of the
clock cycle immediately following the D7 bit. Two clock
cycles after the D7 bit the DAC control register will be
ready to receive the next set of address and data bits.
The clock must be kept running throughout the program-
ming cycle. Internal control circuitry takes care of
ramping the programming voltage for data transfer to the
EEPROM cells. The CAT504’s EEPROM memory cells
will endure over 100,000 write cycles and will retain data
for a minimum of 20 years without being refreshed.
READING DATA
Each time data is transferred into a DAC control register
currently held data is shifted out via the DI pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC’s output. This feature allows µPs to
poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in EEPROM so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low before
the 13^th clock cycle completes. In doing so the EEPROM’s
setting is reloaded into the DAC control register. Since
this value is the same as that which had been there
previously no change in the DAC’s output is noticed.
Had the value held in the control register been different
from that stored in EEPROM then a change would occur
at the read cycle’s conclusion.
Figure 1. Writing to Memory
to 1 2 3 4 5 6 7 8 9 10 11 12
N N+1 N+2
CS
DI
DO
PROG
Vpp
DAC
OUTPUT
NEW DAC DATA
1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DAC DATA
D0 D1 D2 D3 D4 D5 D6 D7
DON'T CARE
CURRENT
DAC VALUE
NON-VOLATILE
NEW
DAC VALUE
VOLATILE
NEW
DAC VALUE
NON-VOLATILE
Figure 2. Reading from Memory
to 1 2 3 4 5 6 7 8 9 10 11 12
CS
DI
DO
PROG
1 A0 A1
CURRENT DAC DATA
D0 D1 D2 D3 D4 D5 D6 D7
Vpp
DAC
OUTPUT
DON'T CARE
CURRENT
DAC VALUE
NON-VOLATILE
Doc. No. 25048-0A 2/98 M-1
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