CAT28F001 Datasheet, PDF (6/18 Pages) Catalyst Semiconductor – 1 Megabit CMOS Boot Block Flash Memory

CAT28F001
A.C. CHARACTERISTICS, Program/Erase Operation
V_CC = +5V ±10%
JEDEC Standard
28F001-70 28F001-90
28F001-12
Symbol Symbol Parameter
Min. Max. Min. Max. Min. Max.
tAVAV
tWC
Write Cycle Time
70
90
120
tAVWH
tAS
Address Setup to WE Going High
35
40
40
tWHAX
tAH
Address Hold Time from WE Going High 10
10
10
tDVWH
tDS
Data Setup Time to WE Going High
35
40
40
tWHDX
tDH
Data Hold Time from WE Going High 10
10
10
tELWL
tCS
CE Setup Time to WE Going Low
0
0
0
tWHEH
tCH
CE Hold Time from WE Going High
0
0
0
tWLWH
tWP
WE Pulse Width
35
40
40
tWHWL
tWPH
WE High Pulse Width
10
10
10
tWHGL
—
Write Recovery Time Before Read
0
0
0
tPHWL
tPS(1)
RP High Recovery to WE Going Low
480
480
480
tPHHWH
tPHS(1) RP VHH Setup to WE Going High
100
100
100
tVPWH
tVPS(1) VPP Setup to WE Going High
100
100
100
tWHQV1
—
Duration of Programming Operations 15
15
15
tWHQV2
—
Duration of Erase Operations (Boot)
1.3
1.3
1.3
tWHQV3
—
Duration of Erase Operations (Parameter) 1.3
1.3
1.3
tWHQV4
—
Duration of Erase Operations (Main)
3
3
3
tQVVL
tVPH(1) VPP Hold from Valid Status Reg Data
0
0
0
tQVPH
tPHH(1) RP VHH Hold from Status Reg Data
0
0
0
tPHBR(1)
—
Boot Block Relock Delay
100
100
100
tGHHWL
—
OE VHH Setup to WE Going Low
480
480
480
tWHGH
—
OE VHH Hold from WE High
480
480
480
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
28F001-15
Min. Max.
150
40
10
40
10
0
0
40
10
0
480
100
100
15
1.3
1.3
3
0
0
100
480
480
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
µs
Sec
Sec
Sec
ns
ns
ns
ns
ns
Doc. No. 25071-00 2/98 F-1
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