CAT24WC32_05 Datasheet, PDF (6/12 Pages) Catalyst Semiconductor – 32K/64K-Bit I2C Serial CMOS EEPROM

CAT24WC32/64
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24WC32/64. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24WC32/64 acknowledges
once more and the Master generates the STOP condi-
tion. At this time, the device begins an internal program-
ming cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24WC32/64 writes up to 32/64 bytes of data, in
a single write cycle, using the Page Write operation.
CAT24WC32/64, Die revision B = 32 byte page.
CAT24WC64, Die revision D = 64 byste page. The page
write operation is initiated in the same manner as the
byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 31/63 additional bytes. After each byte has
been transmitted, CAT24WC32/64 will respond with an
acknowledge, and internally increment the five low order
address bits by one. The high order bits remain un-
changed.
Figure 6. Byte Write Timing
If the Master transmits more than 32/64 bytes before
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
When all 32/64 bytes are received, and the STOP
condition has been sent by the Master, the internal
programming cycle begins. At this point, all received
data is written to the CAT24WC32/64 in a single
write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24WC32/64 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24WC32/64 is still busy with the
write operation, no ACK will be returned. If
CAT24WC32/64 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to V_CC, the entire memory array is
protected and becomes read only. The CAT24WC32/64
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
S
T
DATA
O
P
SDA LINE S
X XX _*
P
A
A
A
A
C
C
C
C
K
K
K
K
24WC32/64 F08
Figure 7. Page Write Timing
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
SDA LINE S
X XX *
A
A
A
C
C
C
K
K
K
* = Don't care bit for 24WC32
X= Don't care bit
DATA
DATA n
S
T
DATA n+31/63 ^O
P
P
A
AA
A
C
CC
C
K
KK
K
24WC32/64 F09
Doc. No. 1039, Rev. G
6
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice