CAT24C02C Datasheet, PDF (6/9 Pages) Catalyst Semiconductor – 2K-Bit Serial E2PROM

CAT24C02C
Figure 5. Slave Address Bits
24C02C _{1 0 1 0 0 0 0 R/W}
the Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT24C02C will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain un-
changed.
If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be overwrit-
ten.
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24C02C in a single write cycle.
Acknowledge Polling
The disabling of the inputs can be used to take advan-
tage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24C02C initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24C02C is still
busy with the write operation, no ACK will be returned.
If the CAT24C02C has completed the write operation,
an ACK will be returned and the host can then proceed
with thenext read or write operation.
READ OPERATIONS
The READ operation for the CAT24C02C is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
The CAT24C02C’s address counter contains the ad-
dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac-
cess data from address N+1. If N=E (where E = 255 for
24WC02), then the clock out data. After the CAT24C02C
receives its slave address information (with the R/W bit
set to one), it issues an acknowledge, then transmits the
8-bit byte requested. The master device does not send
an acknowledge but will generate a STOP condition.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24C02C acknowledge the word
address, the Master device resends the START condi-
tion and the slave address, this time with the R/W bit set
to one. The CAT24C02C then responds with its ac-
knowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the immediate Address READ or Selective READ
operations. After the 24C02C sends initial 8-bit byte
requested, the Master will respond with an acknowledge
which tells the device it requires more data. The
CAT24C02C will continue to output an 8-bit byte for each
acknowledge sent by the Master. The operation is
terminated when the Master fails to respond with an
acknowledge, thus sending the STOP condition.
The data being transmitted from the CAT24C02C is
outputted sequentially with data from address N fol-
lowed by data from address N+1. The READ operation
address counter increments all of the CAT24C02C
address bits so that the entire memory array can be read
during one operation. If more than 255 bytes are read
out, the counter will “wrap around” and continue to clock
out data bytes.
Doc. No. 25086-00 8/99 S-1
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