CAT93HC46 Datasheet, PDF (5/9 Pages) Catalyst Semiconductor – 1-kb High Speed Microwire Serial EEPROM

CAT93HC46
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93HC46
will come out of the high impedance state; after an initial
dummy zero bit, data will be shifted out, MSB first. The
output will toggle on the rising edge of the SK clock and
will be stable after the specified time delay (t_PD0 or t_PD1)
After the 1st data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the CAT93HC46 will automatically increment to the next
address and shift out the next data word. As long as CS
is continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches the end of the address
space, then loops back to address 0. In the sequential
READ mode, only the initial data word is preceeded by
a dummy zero bit; all subsequent data words will follow
without a dummy zero bit.
Write
After receiving a WRITE command, address and data,
the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self-timed clear and data store cycle into the specified
memory location. The clocking of the SK pin is not
necessary after the device has entered the self-timed
mode. (Note 1.) The ready/busy status of the CAT93HC46
can be determined by selecting the device and polling
the DO pin. Since this device features Auto-Clear before
write, it is NOT necessary to erase a memory location
before it is written into.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of t_CSMIN. The falling edge of CS will start the self-timed
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self-timed mode. (Note 1.) The ready/busy
status of the CAT93HC46 can be determined by selecting
the device and polling the DO pin. Once cleared, the
content of a cleared location returns to a logical “1” state.
Figure 2a. Read Instruction Timing
SK
CS
AN AN_—1
A0
DI
11
0
HIGH-Z
tPD0
DO
0
DN DN_—1
tCS _MIN
STANDBY
tHZ
D1 D0
HIGH-Z
Figure 2b. Sequential Read Instruction Timing
SK
1
11
1
111
11
1
1
1
1
1
1
CS
AN AN_–1
A0
DI
11
0
Don't Care
HIGH-Z
DO
Dummy 0
D15 _{. . .} D0
or
D7 _{. . .} D0
Address + 1
D15 _{. . .} D0
or
D7 _{. . .} D0
Address + 2
D15 _{. . .} D0
or
D7 _{. . .} D0
Address + n
D15 _{. . .}
or
D7 _{. . .}
5
Doc. No. 1008, Rev. G