CAT64LC10 Datasheet, PDF (5/12 Pages) Catalyst Semiconductor – 1K/2K/4K-Bit SPI Serial E2PROM

CAT64LC10/20/40
INSTRUCTION SET
Instruction
Opcode
Address
Data
Read
64LC10
10101000
A5 A4 A3 A2 A1 A0 0 0
D15 - D0
64LC20
10101000
A6 A5 A4 A3 A2 A1 A0 0
D15 - D0
64LC40
10101000
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
Write
64LC10
10100100
A5 A4 A3 A2 A1 A0 0 0
D15 - D0
64LC20
10100100
A6 A5 A4 A3 A2 A1 A0 0
D15 - D0
64LC40
Write Enable
ts ^{Write Disable}
[Write All Locations]⁽¹⁾
10100100
10100011
10100000
10100001
A7 A6 A5 A4 A3 A2 A1 A0
XXXXXXXX
XXXXXXXX
XXXXXXXX
D15 - D0
D15–D0
ar _{Figure 1. A.C. Testing Input/Output Waveform} (2)(3(4) _{(CL = 100 pF)}
VCC x 0.8
P _{VCC x 0.2}
INPUT PULSE LEVELS
VCC x 0.7
VCC x 0.3
REFERENCE POINTS
ed ^Note:
(1) (Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications.
(2) Input Rise and Fall Times (10% to 90%) < 10 ns.
u (3) Input Pulse Levels = VCC x 0.2 and VCC x 0.8.
Discontin ^{(4) Input and Output Timing Reference = VCC x 0.3 and VCC x 0.7.}
5
Doc. No. 1021, Rev. C