CAT34WC02_05 Datasheet, PDF (5/10 Pages) Catalyst Semiconductor – 2-kb I2C Serial EEPROM, Serial Presence Detect

CAT34WC02
I²C BUS PROTOCOL
The following defines the features of the I²C bus proto-
col:
and define which device the Master is accessing. Up to
eight CAT34WC02 may be individually addressed by
the system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
(1) Data transfer may be initiated only when the bus is
not busy.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
t _{device, and is defined as a HIGH to LOW transition of}
r _{SDA when SCL is HIGH. The CAT34WC02 monitor the}
SDA and SCL lines and will not respond until this
a condition is met.
STOP Condition
P _{A LOW to HIGH transition of SDA when SCL is HIGH}
determines the STOP condition. All operations must end
with a STOP condition.
d _{DEVICE ADDRESSING}
e _{The Master begins a transmission by sending a START}
condition. The Master then sends the address of the
u _{particular slave device it is requesting. The four most}
significant bits of the 8-bit slave address are fixed
tin ^{(except when accessing the Write Protect Register) as}
1010 for the CAT34WC02 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
After the Master sends a START condition and the slave
address byte, the CAT34WC02 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT34WC02 then performs a Read or a Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT34WC02 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
When the CAT34WC02 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT34WC02 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
n _{Figure 4. Acknowledge Timing}
SCL FROM
1
o_MASTER
8
9
c_{DATA OUTPUT}
FROM TRANSMITTER
is_{DATA OUTPUT}
D ^{FROM RECEIVER}
START
ACKNOWLEDGE
5020 FHD F06
Figure 5. Slave Address Bits
1 0 1 0 A2 A1 A0 R/W Normal Read and Write
DEVICE ADDRESS
0
1
1
0
A2
A1
A0
R/W
Programming the Write
Protect Register
34WC02 F07
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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Doc No. 1003, Rev. O