CAT28C512 Datasheet, PDF (5/10 Pages) Catalyst Semiconductor – 512K-Bit CMOS PARALLEL E2PROM

Advanced
A.C. CHARACTERISTICS, Write Cycle
V_CC=5V+10%, unless otherwise specified
Symbol Parameter
28C512/513-12 28C512/513-15
Min. Max. Min. Max. Units
tWC
Write Cycle Time
5
5 ms
tAS
Address Setup Time
0
0
ns
tAH
tCS
tCH
tCW(3)
tOES
tOEH
tWP(3)
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
50
50
ns
0
0
ns
0
0
ns
100
100
ns
0
0
ns
0
0
ns
100
100
ns
tDS
Data Setup Time
50
50
ns
tDH
Data Hold Time
0
0
ns
tINIT(1) Write Inhibit Period After Power-up 5
10 5 10 ms
tBLC(1)(4) Byte Load Cycle Time
0.1 100 0.1 100 µs
CAT28C512/513
Figure 1. A.C. Testing Input/Output Waveform(2)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
5096 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
DEVICE
UNDER
TEST
3.3K
OUT
CL = 100 pF
5096 FHD F04
Note:
CL INCLUDES JIG CAPACITANCE
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t_BLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within t_BLC max. stops the timer.
5
Doc. No. 25074-00 2/98