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| CAT1021_07 Datasheet, PDF (5/21 Pages) Catalyst Semiconductor – Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer | |||
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CAT1021, CAT1022, CAT1023
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol
COUT(1)
CIN(1)
Test
Output Capacitance
Input Capacitance
Test Conditions
VOUT = 0V
VIN = 0V
Max Units
8
pF
6
pF
AC CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle(2)
Symbol Parameter
Min
Max Units
fSCL
Clock Frequency
400
kHz
tSP
Input Filter Spike Suppression (SDA, SCL)
100
ns
tLOW Clock Low Period
1.3
µs
tHIGH
tR(1)
tF(1)
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
0.6
µs
300
ns
300
ns
tHD; STA Start Condition Hold Time
0.6
µs
tSU; STA Start Condition Setup Time (for a Repeated Start)
0.6
µs
tHD; DAT Data Input Hold Time
0
ns
tSU; DAT Data Input Setup Time
100
ns
tSU; STO Stop Condition Setup Time
0.6
µs
tAA
SCL Low to Data Out Valid
900
ns
tDH
Data Out Hold Time
50
ns
tBUF(1) Time the Bus must be Free Before a New Transmission Can Start
1.3
µs
tWC(3) Write Cycle Time (Byte or Page)
5
ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to âAC Test Conditionsâ table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© 2007 Catalyst Semiconductor, Inc.
5
Characteristics subject to change without notice
Doc. No. 3009 Rev. L
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