CAT514 Datasheet, PDF (4/11 Pages) Catalyst Semiconductor – 8-Bit Quad Digital POT

to
1
2
3
4
5
CLK
tCLK H
tCSS
CS
tDIS
DI
tDIH
tCLK L
tCSH
tCSMIN
DO
PROG
RDY/BSY
tLZ
tDO1
to
1
2
tDO0
tHZ
tPS
tPROG
3
tBUSY
4
5
PARAM
NAME
FROM
TIMING
MIN/MAX
TO
tCLK H Rising CLK edge to falling CLK edge
Min
tCLK L Falling CLK edge to CLK rising edge
Min
tCSH Falling CLK edge for last data bit (DI)
Min
to falling CS edge
tCSS Rising CS edge to next rising CLK edge
Min
tCSMIN Falling CS edge to rising CS edge
Min
tDIS Data valid to first rising CLK
Min
edge after CS = high
tDIH Rising CLK edge to end of data valid
tDO0 Rising CLK edge to D0 = low
tLZ
Rising CS edge to D0 becoming high
low impedance (active output)
Min
Max
(Max)
tDO1
tHZ
Rising CLK edge to D0 = high
Falling CS edge to D0 becoming high
impedance (Tri-State)
tPS _{Rising PROG edge to next rising}
CLK edge
tPROG _{Rising PROG edge to falling}
PROG edge
tBUSY Falling CLK edge after PROG=H to
rising RDY/BSY edge
Max
(Max)
Min
Min
Max