CAT310_07 Datasheet, PDF (4/11 Pages) Catalyst Semiconductor – 10 Channel Automotive LED Display Driver

CAT310
PIN DESCRIPTIONS
VCC is the supply input for the internal logic
BLANK is the CMOS logic input (active high)
and is compatible with both 3.3V and 5V
used to temporarily disable all outputs. An
systems. The logic is held in a reset state until
internal pull-up current of 10 microampere is
VCC exceeds 2.5V. It is recommended that a
present on this pin. The BLANK pin must be
small bypass ceramic capacitor (1uF) be
driven to a logic low in order for channel outputs
placed between VCC and GND pins on the
to resume normal operation. An external pull-
device.
down resistance of 10kΩ or less is adequate for
SIN is the CMOS logic pin for delivering the
logic low.
serial input data stream into the internal 10-bit
SOUT is the CMOS logic output used for daisy
shift register. The most recent or last data
chain applications. The serial output data
value in the serial stream is used to configure
stream is fed from the last stage of the internal
the state of output channel “zero” (OUT0).
10-bit shift register. On each rising edge of the
During the initial power up sequence all
clock, the SOUT value will be updated. The
contents of the shift register are reset and
data value present on this pin is identical to the
cleared to zero.
data value being used for configuring the state
SCLK is the CMOS logic pin used to clock
of output channel nine (OUT9). At initial power
up, the SOUT data stream will contain all
the internal shift register. On each rising edge
zeroes until the shift register has been fully
of clock, the serial data will advance through
loaded.
one stage of the shift register.
XLAT is the CMOS logic input used to
transfer data from the 10-bit shift register into
the output channel latches. An internal pull-
down current of 10 microampere is present on
this pin. When XLAT is low, the state of each
output channel remains unchanged. When
XLAT is driven high, the contents of the shift
VBATT input monitors the battery voltage. If an
over-voltage, above 19V typical, is detected, all
outputs are disabled. Upon conclusion of the
over-voltage condition, all outputs resume
normal operation. The current drawn by the
VBATT pin is less than 1 microampere during
normal operation.
register appear at their respective output
channels. An external pull-up resistance of
10kΩ or less is adequate for logic high.
OUT0-OUT9 are the ten LED outputs
connected internally to the switch N-channel
FETs. They sink currents up to 50mA per
PGND, GND pins should be connected to
the ground on the PCB.
channel and can withstand transients up to 40V
compatible with automotive “load dump”. The
output on-resistance is 5Ω, and the off-
resistance is 5MΩ.
PIN TABLE
Pin Number Pin Name
Description/Function
1
SCLK
Clock input for the data shift register.
2
XLAT
Control input for the data latch.
3
SIN
Serial data input.
4
SOUT
Serial data output.
5
GND
Ground.
6-10
OUT4 - OUT0 Open drain outputs.
11-15
OUT9 - OUT5 Open drain outputs.
16
PGND
Ground for LED driver outputs.
17
VBATT
Battery sense input.
18
VCC
Power supply voltage for the logic
19
BLANK
Blank input. When BLANK is high, all the output drivers are turned off.
20
N.C.
No connect.
© Catalyst Semiconductor, Inc.
4
Characteristics subject to change without notice
Doc No. 25087, Rev. 1