CAT24WC129 Datasheet, PDF (4/8 Pages) Catalyst Semiconductor – 128K-Bit I2C Serial CMOS E2PROM

CAT24WC129
Preliminary
PIN DESCRIPTIONS
I²C BUS PROTOCOL
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the top
1/4 array of memory (locations 3000H to 3FFFH) is write
protected. When left floating, memory is unprotected.
The features of the I²C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC129 monitors
the SDA and SCL lines and will not respond until this
condition is met.
Figure 1. Bus Timing
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
tF
tHIGH
tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
SDA OUT
tAA
tDH
Figure 2. Write Cycle Timing
tBUF
5020 FHD F03
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 25065-00 6/99 S-1
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
STOP BIT
5020 FHD F05
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