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| CAT1320_08 Datasheet, PDF (4/18 Pages) Catalyst Semiconductor – Supervisory Circuits with I2C Serial 32K CMOS EEPROM | |||
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CAT1320, CAT1321
CAPACITANCE
TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test
COUT(1) Output Capacitance
CIN(1)
Input Capacitance
Test Conditions
VOUT = 0V
VIN = 0V
Max
8
6
Units
pF
pF
A.C. CHARACTERISTICS
VCC = 3.0V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle2
Symbol
Parameter
Min
Max
Units
fSCL
Clock Frequency
tSP1
Input Filter Spike
Suppression (SDA, SCL)
400
kHz
100
ns
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
0.6
µs
tR1
SDA and SCL Rise Time
300
ns
tF1
SDA and SCL Fall Time
300
ns
tHD;STA
Start Condition Hold Time
0.6
µs
tSU;STA
Start Condition Setup Time
(for a Repeated Start)
0.6
µs
tHD;DAT
Data Input Hold Time
0
ns
tSU;DAT
Data Input Setup Time
100
ns
tSU;STO
Stop Condition Setup Time
0.6
µs
tAA
SCL Low to Data Out Valid
900
ns
tDH
Data Out Hold Time
50
ns
t1
BUF
Time the Bus must be Free Before a
New Transmission Can Start
1.3
µs
tWC3
Write Cycle Time (Byte or Page)
5
ms
Notes:
1. This parameter is characterized initially and after a design or process change that affects
the parameter. Not 100% tested.
2. Test Conditions according to âAC Test Conditionsâ table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of
the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled,
SDA is allowed to remain high and the device does not respond to its slave address.
Doc. No. MD-3014, Rev. B
4
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