CAT93CXXXX Datasheet, PDF (3/10 Pages) Catalyst Semiconductor – Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer

Advanced Information
CAT93CXXXX
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
NEND(1)
TDR(1)
VZAP(1)
I_LTH(1)(3)
Endurance
Data Retention
ESD Susceptibility
Latch-up
1,000,000
100
2000
100
Max. Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
A.C. CHARACTERISTICS
V_CC=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF
SYMBOL PARAMETER
tCSS
CS Setup Time
tCSH
CS Hold Time
tDIS
DI Setup Time
tDIH
DI Hold Time
tPD1
Output Delay to 1
tPD0
tHZ(1)
Output Delay to 0
Output Delay to High-Z
tEW
Program/Erase Pulse Width
tCSMIN
Minimum CS Low Time
tSKHI
Minimum SK High Time
tSKLOW Minimum SK Low Time
tSV
Output Delay to Status Valid
SKMAX Maximum Clock Frequency
VCC =
2.7V -6V
Min. Max.
250
0
250
250
0.5
0.5
500
5
0.5
0.5
0.5
0.5
DC 1000
Limits
VCC =
4.5V-5.5V
Test
Min. Max. UNITS Conditions
50
ns
0
ns
50
ns
50
ns
0.1 µs
0.1 µs
C_L = 100pF
100 ns
5
ms
0.1
µs
0.1
µs
0.1
µs
0.1 µs
DC 3000 KHZ
Power-Up Timing⁽¹⁾⁽²⁾
Symbol
t_PUR
tPUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
CAPACITANCE T_A = 25°C, f = 1.0 MHz, V_CC = 5V
Symbol Test
Max.
Units
CI/O(1)
CIN(1)
Input/Output Capacitance
Input Capacitance
8
pF
6
pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
(3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V_CC +1V.
Conditions
VI/O = 0V
VIN = 0V
9-87
Stock No. 21084-01 2/98