CAT93C46R Datasheet, PDF (3/13 Pages) Catalyst Semiconductor – 1-Kb Microwire Serial EEPROM

CAT93C46R
PIN CAPACITANCE
Symbol
Test
C_OUT(1)
Output Capacitance (DO)
C_IN(1)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V_OUT = 0V
V_IN = 0V
Max
Units
5
pF
5
pF
A.C. CHARACTERISTICS⁽²⁾
Symbol
tCSS
tCSH
tDIS
tDIH
tPD1
tPD0
tHZ(1)
tEW
tCSMIN
tSKHI
tSKLOW
tSV
SKMAX
Parameter
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
VCC = 1.8V- 5.5V
Min
Max
50
0
100
100
0.25
0.25
100
5
0.25
0.25
0.25
0.25
DC
2
VCC = 4.5V- 5.5V
Min
Max
50
0
50
50
0.1
0.1
100
5
0.1
0.1
0.1
0.1
DC
4
Units
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
MHz
POWER-UP TIMING ⁽¹⁾⁽³⁾
Symbol
tPUR
tPUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤ 50ns
0.4V to 2.4V
4.5V ≤ VCC ≤ 5.5V
0.8V, 2.0V
4.5V ≤ VCC ≤ 5.5V
0.2VCC to 0.7VCC
1.8V ≤ VCC ≤ 4.5V
0.5VCC
1.8V ≤ VCC ≤ 4.5V
Current Source IOLmax/IOHmax; CL = 100pF
NOTE:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(2) Test conditions according to “A.C. Test Conditions” table.
(3) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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Doc No. 1107, Rev. F