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CAT25C32 Datasheet, PDF (3/9 Pages) Catalyst Semiconductor – 32K/64K-Bit SPI Serial CMOS E2PROM
Advanced Information
CAT25C32/64
Figure 1. Sychronous Data Timing
VIH
CS
SCK
VIL
tCSS
VIH
VIL
VIH
SI
VIL
tWH
tSU
tH
VALID IN
VOH
SO
VOL
HI-Z
Note: Dashed Line= mode (1, 1) — — — —
A.C. CHARACTERISTICS
tCS
tCSH
tWL
tRI
tFI
tV
tHO
tDIS
HI-Z
SYMBOL PARAMETER
Vcc=
1.8V-6.0V
Min. Max.
Limits
VCC =
2.5V-6.0V
Min. Max.
VCC =
4.5V-5.5V
Min. Max.
tSU
Data Setup Time
50
50
20
tH
Data Hold Time
50
50
20
tWH
SCK High Time
250
125
40
tWL
SCK Low Time
250
125
40
fSCK
tLZ
tRI(1)
tFI(1)
tHD
tCD
Clock Frequency
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
DC
1 DC
3
DC 10
50
50
50
2
2
2
2
2
2
100
100
40
100
100
40
tWC
Write Cycle Time
10
10
5
tV
Output Valid from Clock Low
250
250
80
tHO
Output Hold Time
0
0
0
tDIS
Output Disable Time
tHZ
HOLD to Output High Z
tCS
CS High Time
tCSS
CS Setup Time
tCSH
CS Hold Time
250
250
75
150
100
50
500
250
200
500
250
100
500
250
100
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Test
UNITS Conditions
ns
ns
ns
ns
MHz
ns
µs
µs CL = 50pF
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
3
Doc No. 25087 -00 8/99 SPI-1