CAT24WC257 Datasheet, PDF (3/10 Pages) Catalyst Semiconductor – 256K-Bit I2C Serial CMOS EEPROM

CAT24WC257
A.C. CHARACTERISTICS
V_CC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter
V_CC=1.8V - 6.0V V_CC=2.5V - 6.0V V_CC=3.0V - 5.5V
Min Max Min Max Min Max
F_SCL
Clock Frequency
100
400
1000
t_AA
SCL Low to SDA Data Out
and ACK Out
0.1 3.5
0.05 0.9
0.05 0.55
t_BUF(1) Time the Bus Must be Free Before 4.7
1.2
0.5
a New Transmission Can Start
t_HD:STA Start Condition Hold Time
4.0
0.6
0.25
t_LOW
Clock Low Period
4.7
1.2
0.6
t_HIGH
Clock High Period
4.0
0.6
0.4
t_SU:STA Start Condition Setup Time
4.0
0.6
(for a Repeated Start Condition)
0.25
t_HD:DAT Data In Hold Time
0
0
0
t_SU:DAT
t_R(1)
t_F(1)
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
100
1.0
300
100
0.3
300
100
0.3
100
tSU:STO Stop Condition Setup Time
4.7
0.6
0.25
tDH
Data Out Hold Time
100
50
50
tWR
Write Cycle Time
10
10
10
Units
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
Power-Up Timing ⁽²⁾⁽³⁾
Symbol Parameter
t_PUR Power-Up to Read Operation
t_PUW Power-Up to Write Operation
Min Typ
Note:
(1) AC measurement conditions:
RL (connects to V_CC): 0.3V_CC to 0.7 V_CC
Input rise and fall times: < 50ns
Input and output timeing reference voltages: 0.5 V_CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
Max
1
1
Units
ms
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
3
Doc. No. 1030, Rev. E