CAT24FC256 Datasheet, PDF (3/12 Pages) Catalyst Semiconductor – 256K-Bit I2C Serial CMOS EEPROM

CAT24FC256
AC CHARACTERISTICS
V_CC = 1.8V to 5.5 V, unless otherwise specified. Output load is 1 TTL gate and 100pF.
Read & Write Cycle Limits
Symbol Parameter
VCC=1.8V - 5.5V
VCC=2.5V - 5.5V
Min
Max
Min
Max
Units
F_SCL
t_AA
t ⁽²⁾
BUF
Clock Frequency
SCL Low to SDA Data Out and
ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
t_HD:STA Start Condition Hold Time
t_LOW
Clock Low Period
t_HIGH
t_SU:STA
Clock High Period
Start Condition Setup Time (for a
Repeated Start Condition)
t_HD:DAT Data In Hold Time
t
SU:DAT
t ⁽²⁾
R
t ⁽²⁾
F
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
t_SU:STO Stop Condition Setup Time
t_DH
Data Out Hold Time
t_WR
Write Cycle Time
t_SP
Input Suppresssion (SDA, SCL)
t_SU;WP
WP Setup Time
t_HD;WP
WP Hold Time
Power-Up Timing ⁽²⁾⁽³⁾
Symbol
Parameter
0.05
1.3
0.6
1.3
0.6
0.6
0
100
20
20
0.6
50
0.6
1.3
400
1000
kHz
0.9
0.05
0.5
µs
0.5
µs
0.25
µs
0.6
µs
0.4
µs
0.25
µs
0
ns
100
ns
0.3
0.1
µs
300
100
ns
0.25
µs
50
ns
5
5
ms
50
50
ns
0.5
µs
0.8
µs
Min
Typ
Max
Units
t_PUR
Power-Up to Read Operation
1
ms
t_PUW
Power-Up to Write Operation
1
ms
Note:
(1) AC measurement conditions:
RL (connects to V_CC): 0.3V_CC to 0.7 V_CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V_CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
3
Doc. No. 1040, Rev. J