CAT24FC01 Datasheet, PDF (3/10 Pages) Catalyst Semiconductor – 1-kb I2C Serial EEPROM

CAT24FC01
A.C. CHARACTERISTICS
V_CC = 1.8 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
FSCL
TI(1)
tAA
tBUF(1)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR(1)
t_F(1)
t_SU:STO
t_DH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1.8 V - 5.5 V
Min Max
0
100
100
3.5
4.7
4
4.7
4
4.7
0
250
1
300
4
100
2.5 V - 5.5 V
Min
Max
0
400
100
0.9
1.3
0.6
1.3
0.6
0.6
0
100
0.3
300
0.6
100
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Power-Up Timing⁽¹⁾⁽²⁾
Symbol
Parameter
tPUR
t_PUW
Power-up to Read Operation
Power-up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Write Cycle Limits
Symbol
Parameter
t_WR
Write Cycle Time
Min
Typ
Max
5
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
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Doc No. 1073, Rev. D