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| 93C57 Datasheet, PDF (3/9 Pages) Catalyst Semiconductor – 2K-Bit Microwire Serial EEPROM | |||
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CAT93C56/57
PIN CAPACITANCE
Symbol
Test
Conditions Min
Typ
Max Units
COUT(2)
CIN(2)
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
VOUT=0V
VIN=0V
5
pF
5
pF
INSTRUCTION SET
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Device
Type
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
93C56(1)
93C57
Start
Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Opcode
10
10
11
11
01
01
00
00
00
00
00
00
00
00
Address
x8
A8-A0
A7-A0
A8-A0
A7-A0
A8-A0
A7-A0
x16
A7-A0
A6-A0
A7-A0
A6-A0
A7-A0
A6-A0
11XXXXXXX 11XXXXXX
11XXXXXX 11XXXXX
00XXXXXXX 00XXXXXX
00XXXXXX 00XXXXX
10XXXXXXX 10XXXXXX
10XXXXXX 10XXXXX
01XXXXXXX 01XXXXXX
01XXXXXX 01XXXXX
Data
x8
x16
Comments
Read Address ANâ A0
Clear Address ANâ A0
D7-D0
D7-D0
D15-D0 Write Address ANâ A0
D15-D0
Write Enable
Write Disable
Clear All Addresses
D7-D0 D15-D0 Write All Addresses
D7-D0 D15-D0
A.C. CHARACTERISTICS
Symbol Parameter
Test
Conditions
VCC =
1.8V-6V
Limits
VCC =
2.5V-6V
VCC =
4.5V-5.5V
Min Max Min Max Min Max
Units
tCSS
CS Setup Time
200
100
50
ns
tCSH
CS Hold Time
0
0
0
ns
tDIS
DI Setup Time
400
200
100
ns
tDIH
DI Hold Time
400
200
100
ns
tPD1
Output Delay to 1
1
0.5
0.25 µs
tPD0
Output Delay to 0
CL = 100pF
1
0.5
0.25 µs
tHZ(1)
Output Delay to High-Z
(3)
400
200
100
ns
tEW
Program/Erase Pulse Width
10
10
10
ms
tCSMIN
Minimum CS Low Time
1
0.5
0.25
µs
tSKHI
Minimum SK High Time
1
0.5
0.25
µs
tSKLOW Minimum SK Low Time
1
0.5
0.25
µs
tSV
Output Delay to Status Valid
1
0.5
0.25 µs
SKMAX Maximum Clock Frequency
DC 250 DC 500 DC 1000 kHz
Note:
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE
and ERASE commands.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
3
Doc. No. 1088, Rev. M
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