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CAT513 Datasheet, PDF (2/10 Pages) Catalyst Semiconductor – 8-Bit Dual Digital POT | |||
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CAT513
Advance Information
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage
VDD to GND ...................................... â0.5V to +7V
Inputs
CLK to GND ............................ â0.5V to VDD +0.5V
CS to GND .............................. â0.5V to VDD +0.5V
DI to GND ............................... â0.5V to VDD +0.5V
PROG to GND ........................ â0.5V to VDD +0.5V
VREFH to GND ........................ â0.5V to VDD +0.5V
VREFL to GND ......................... â0.5V to VDD +0.5V
Outputs
D0 to GND ............................... â0.5V to VDD +0.5V
VOUT 1â 3 to GND ................... â0.5V to VDD +0.5V
Operating Ambient Temperature
Commercial (âCâ suffix) .................... 0°C to +70°C
Industrial (âIâ suffix) ...................... â 40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ....................... â65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol Parameter
Min
Max
Units
Test Method
VZAP(1)
ILTH(1)(2)
ESD Susceptibility
Latch-Up
2000
100
Volts
mA
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Notes: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from â1V to VCC + 1V.
DC ELECTRICAL CHARACTERISTICS:
VDD = +2.7 to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
Max Units
Accuracy
INL
Resolution
Integral Linearity Error
DNL
Differential Linearity Error
8
ILOAD = 250 nA, TR = C
â
TR = I
â
ILOAD = 1 µA, TR = C
â
TR = I
â
ILOAD = 250 nA, TR = C
â
TR = I
â
ILOAD = 1 µA, TR = C
â
TR = I
â
â
â
Bits
â
±1
LSB
â
±1
LSB
â
±2
LSB
â
±2
LSB
â
± 0.5 LSB
â
± 0.5 LSB
â
± 1.5 LSB
â
± 1.5 LSB
Logic Inputs
IIH
Input Leakage Current
IIL
Input Leakage Current
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
References
VRH
VREFH Input Voltage Range
VRL
VREFL Input Voltage Range
ZIN
VREFHâVREFL Resistance
Logic Outputs
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VIN = VDD
VIN = 0V
â
â
10
µA
â
â
â10
µA
2
â
VDD
V
0
â
0.8
V
2.7
GND
â
â
VDD
V
â
VDD -2.7 V
7k
â
â¦
IOH = â 40 µA
VDD â0.3
â
IOL = 1 mA, VDD = +5V
â
â
IOL = 0.4 mA, VDD = +3V
â
â
â
V
0.4
V
0.4
V
Doc. No. ________ 3/01 M-1
2
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