CAT512 Datasheet, PDF (2/10 Pages) Catalyst Semiconductor – 8-Bit Dual Digital POT with Independent Reference Inputs

CAT512
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
V_DD to GND ...................................... –0.5V to +7V
Inputs
CLK to GND ............................ –0.5V to V_DD +0.5V
CS to GND .............................. –0.5V to V_DD +0.5V
DI to GND ............................... –0.5V to V_DD +0.5V
RDY/BSY to GND ................... –0.5V to V_DD +0.5V
PROG to GND ........................ –0.5V to V_DD +0.5V
V_REFH to GND ........................ –0.5V to V_DD +0.5V
V_REFL to GND ......................... –0.5V to V_DD +0.5V
Outputs
D₀ to GND ............................... –0.5V to V_DD +0.5V
V_OUT 1– 2 to GND ................... –0.5V to V_DD +0.5V
Advanced Information
Operating Ambient Temperature
Commercial (‘C’ suffix) .................... 0°C to +70°C
Industrial (‘I’ suffix) ...................... – 40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ....................... –65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol
V_ZAP(1)
I_LTH(1)(2)
Parameter
ESD Susceptibility
Latch-Up
Min
2000
100
Max
Units
Volts
mA
Test Method
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Notes: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V_CC + 1V.
DC ELECTRICAL CHARACTERISTICS: V_DD = +2.7V to +5.5V, V_REFH = V_DD, V_REFL = 0V, unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
Max Units
Accuracy
INL
Resolution
Integral Linearity Error
DNL
Differential Linearity Error
Logic Inputs
I_IH
Input Leakage Current
I_IL
Input Leakage Current
V_IH
High Level Input Voltage
V_IL
Low Level Input Voltage
References
V_RH
V_REFH Input Voltage Range
V_RL
V_REFL Input Voltage Range
Z_IN
V_REFH–V_REFL Resistance
∆V_IN / R_IN Input Resistance Match
Logic Outputs
V_OH
High Level Output Voltage
V_OL
Low Level Output Voltage
8
—
—
Bits
I_LOAD = 250 nA, T_R = C
—
T_R = I
—
I_LOAD = 1 µA, T_R = C
—
T_R = I
—
I_LOAD = 250 nA, T_R = C
—
T_R = I
—
I_LOAD = 1 µA, T_R = C
—
T_R = I
—
V_IN = V_DD
—
V_IN = 0V
—
2
0
0.6
±1
LSB
0.6
±1
LSB
1.2
—
LSB
1.2
—
LSB
0.25
± 0.5 LSB
0.25
± 0.5 LSB
0.5
—
LSB
0.5
—
LSB
—
10
µA
—
–10
µA
—
V_DD
V
—
0.8
V
2.7
GND
—
—
—
—
28K
± 0.5
V_DD
V
V_DD -2.7 V
—
Ω
±1
%
I_OH = – 40 µA
V_DD–0.3
—
I_OL = 1 mA, V_DD = +5V
—
—
I_OL = 0.4 mA, V_DD = +3V
—
—
—
V
0.4
V
0.4
V
8/00
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