English
Language : 

CAT24C32 Datasheet, PDF (2/18 Pages) Catalyst Semiconductor – 32-Kb I2C CMOS Serial EEPROM
◁
CAT24C32
ABSOLUTE MAXIMUM RATINGS(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground(2)
-65°C to +150°C
-0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS(3)
Symbol
NEND(4)
TDR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
Test Conditions
ICCR
ICCW
ISB
IL
Read Current
Write Current
Standby Current
I/O Pin Leakage
Read, fSCL = 400 kHz
Write, fSCL = 400 kHz
All I/O Pins at GND or VCC
Pin at GND or VCC
VIL
VIH
VOL1
VOL2
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
VCC ≥ 2.5 V, IOL = 3.0 mA
VCC < 2.5 V, IOL = 1.0 mA
Min
Max
1
1
1
1
-0.5 VCC x 0.3
VCC x 0.7 VCC + 0.5
0.4
0.2
Units
mA
mA
μA
μA
V
V
V
V
PIN IMPEDANCE CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
Conditions
Max Units
CIN(3) SDA I/O Pin Capacitance
VIN = 0 V
8
pF
CIN(3)
IWP(5)
Input Capacitance (other pins)
WP Input Current
VIN = 0 V
VIN < VIH
VIN > VIH
6
pF
100
μA
1
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
Doc. No. 1101, Rev. G
2
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
 ▷