CAT28F010_04 Datasheet, PDF (13/15 Pages) Catalyst Semiconductor – 1 Megabit CMOS Flash Memory

CAT28F010
Program-Verify Mode
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stays latched until the verify is completed. The Program-
verify operation is initiated by writing C0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify V_CC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
Abort/Reset
An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two
consecutive program cycles with FFH on the data bus
will abort an erase or a program operation. The abort/
reset operation can interrupt at any time in a program or
erase operation and the device is reset to the Read
Mode.
POWER UP/DOWN PROTECTION
The CAT28F010 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and VCC
may power up in any order. Additionally VPP may be
hardwired to VPPH independent of the state of VCC and
any power up/down cycling. The internal command
register of the CAT28F010 is reset to the Read Mode on
power up.
POWER SUPPLY DECOUPLING
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitor between VCC and VSS and VPP and VSS. These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
Figure 8. Alternate A.C. Timing for Program Operation
VCC POWER-UP SETUP PROGRAM LATCH ADDRESS
& STANDBY
COMMAND
& DATA
PROGRAM
VERIFY
PROGRAMMING COMMAND
PROGRAM VCC POWER-DOWN/
VERIFICATION
STANDBY
ADDRESSES
tWC
tWC
tAVEL
tELAX
WE ^((WE))
tWLEL
tEHWH
tWLEL
tEHWH
tWLEL
tEHWH
OE (G)
tGHEL
tEHEL
tEHEH
tEHGL
CE (EW))
DATA (I/O)
tDVEH
HIGH-Z
DATA IN
= 40H
tEHDX
tELEH
tELEH
tEHDX
tDVEH
tDVEH
DATA IN
VCC ^5.0V
0V
VPP ^VPPH
VPPL
tVPEL
DATA IN
= C0H
tOE
tEHDX
tOLZ
tLZ
tCE
tRC
tEHQZ
tDF
tOH
VALID
DATA OUT
28F010 F10
13
Doc. No. 1019, Rev. D