CAT5411 Datasheet, PDF (1/16 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and SPI Interface

CAT5411
Dual Digitally Programmable Potentiometers (DPP™) with
64 Taps and SPI Interface
FEATURES
ALOGEN ^FR
LEAD
F
R
E
E
TM
s Two linear-taper digitally programmable
potentiometers
s 64 resistor taps per potentiometer
s End to end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ
s Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
s Low wiper resistance, typically 80Ω
s Nonvolatile memory storage for up to four wiper
settings for each potentiometer
DESCRIPTION
s Automatic recall of saved wiper settings at
power up
s 2.5 to 6.0 volt operation
s Standby current less than 1µA
s 1,000,000 nonvolatile WRITE cycles
s 100 year nonvolatile memory data retention
s 24-lead SOIC, 24-lead TSSOP, and BGA
s Industrial temperature ranges
The CAT5411 is two Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the
two potentiometers is automatically loaded into its
respective wiper control register.
The CAT5411 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC Package (J, W)
TSSOP Package (U, Y)
VCC
RL0
RH0
RW0
CS
WP
SI
A1
RL1
RH1
RW1
GND
1
24
2
23
3
22
4
21
5
20
6 _CAT 19
7 ⁵⁴¹¹ 18
8
17
9
16
10
15
11
14
12
13
NC
SI
NC
A1
NC
RL1
NC
RH1
A0
RW1
SO GND
HOLD NC
SCK
NC
NC
NC
NC
NC
NC
SCK
NC HOLD
1
24
2
23
3
22
4
21
5
20
6 _CAT 19
7 ⁵⁴¹¹ 18
8
17
9
16
10
15
11
14
12
13
WP
CS
RW0
RH0
RL0
VCC
NC
NC
NC
NC
A0
SO
FUNCTIONAL DIAGRAM
CS
SCK
SI
SO
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
WP
CONTROL
A0
LOGIC
A1
NONVOLATILE
DATA
REGISTERS
A
B
BGA ^C
D
E
F
1
RW0
RL0
VCC
NC
NC
NC
2
3
CS
A1
WP
SI
RH0 RH1
NC
NC
SO HOLD
A0 SCK
4
RL1
RW1
VSS
NC
NC
NC
Top View - Bump Side Down
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
RH0 RH1
R _W0
R _W1
RL0 RL1
Document No. 2114, Rev. G