CAT5251 Datasheet, PDF (1/15 Pages) Catalyst Semiconductor – Quad Digitally Programmable Potentiometer (DPP) with 256 Taps and SPI Interface

CAT5251
Quad Digitally Programmable Potentiometer (DPP™) with
256 Taps and SPI Interface
FEATURES
ALOGEN ^FR
LEA _{D F REETM}
s Four linear-taper digitally programmable
potentiometers
s 256 resistor taps per potentiometer
s End to end resistance 50kΩ or 100kΩ
s Potentiometer control and memory access via
SPI interface
s Low wiper resistance, typically 100Ω
s Nonvolatile memory storage for up to four wiper
settings for each potentiometer
DESCRIPTION
s Automatic recall of saved wiper settings at
power up
s 2.5 to 6.0 volt operation
s Standby current less than 1µA
s 1,000,000 nonvolatile WRITE cycles
s 100 year nonvolatile memory data retention
s 24-lead SOIC and 24-lead TSSOP
s Industrial temperature range
The CAT5251 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 8-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 8-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the
four potentiometers is automatically loaded into its
respective wiper control register.
The CAT5251 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40°C to 85°C industrial
operating temperature range and offered in a 24-lead
SOIC and TSSOP package.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
SOIC/TSSOP Package (J, W/U, Y)
SO
A0
RW3
RH3
RL3
NC
VCC
RL0
RH0
RW0
CS
WP
1
24
2
23
3
22
4
21
5
20
6 _CAT 19
7 ⁵²⁵¹ 18
8
17
9
16
10
15
11
14
12
13
HOLD
SCK
RL2
RH2
RW2
NC
GND
RW1
RH1
RL1
A1
SI
RH0 RH1 RH2 RH3
CS
SCK
SI
SO
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
WP
A0
A1
HOLD
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R _W0
R _W1
R _W2
R _W3
RL0 RL1 RL2 RL3
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Document No. 2017, Rev. D