CAT33C804A Datasheet, PDF (1/14 Pages) Catalyst Semiconductor – 4K-Bit Secure Access Serial E2PROM

Preliminary
CAT33C804A
4K-Bit Secure Access Serial E²PROM
FEATURES
s Single 3V Supply
s Password READ/WRITE Protection: 1 to 8 Bytes
s Memory Pointer WRITE Protection
s Sequential READ Operation
s 256 x 16 or 512 x 8 Selectable Serial Memory
s UART Compatible Asynchronous Protocol
s Commercial, Industrial and Automotive
Temperature Ranges
s 100,000 Program/Erase Cycles
s I/O Speed: 9600 Baud
–Clock Frequency: 4.9152 MHz Xtal
s Low Power Consumption:
–Active: 3 mA
–Standby: 250 µA
s 100 Year Data Retention
DESCRIPTION
The CAT33C804A is a 4K-bit Serial E²PROM that safe-
guards stored data from unauthorized access by use of
a user selectable (1 to 8 byte) access code and a
movable memory pointer. Two operating modes provide
unprotected and password-protected operation allow-
ing the user to configure the device as anything from a
ROM to a fully protected no-access memory. The
CAT33C804A uses a UART compatible asynchronous
protocol and has a Sequential Read feature where data
can be sequentially clocked out of the memory array.
The device is available in 8-pin DIP or 16-pin SOIC
packages.
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
CS 1
CLK 2
8 VCC
7 PE
NC 1
NC 2
DI 3
6 ERR
CS 3
DO 4
5 GND CLK 4
DI 5
DO 6
NC 7
NC 8
PIN FUNCTIONS
Pin Name
Function
16 NC
15 NC
14
VCC
13 PE
12 ERR
11
GND
10 NC
9 NC
5074 FHD F01
CS
Chip Select
DO⁽¹⁾
Serial Data Output
CLK
Clock Input
DI⁽¹⁾
Serial Data Input
PE
Parity Enable
ERR
Error Indication Pin
VCC
+3V Power Supply
GND
Ground
Note:
(1) DI, DO may be tied together to form a common I/O.
BLOCK DIAGRAM
VCC
GND
DO
CLK
SERIAL
COMMUNI-
PE
CATION
CS
BLOCK
DI
ERR
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
STATUS
REGISTER
64-BIT ACCESS CODE
&
CONTROL BLOCK
4K-BIT EEPROM
ARRAY
R/W
ADDRESS
BUFFER DECODER
ADDRESS
REGISTER
MEMORY
POINTER
33C804 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25044-00 2/98