CAT1640_07 Datasheet, PDF (1/18 Pages) Catalyst Semiconductor – Supervisory Circuits with I2C Serial 64K CMOS EEPROM

CAT1640, CAT1641
Supervisory Circuits with I²C Serial 64K CMOS EEPROM
ALOGEN ^FR
LEA _{D F REETM}
FEATURES
s Precision power supply voltage monitor
— 5V, 3.3V and 3V systems
- +5.0V (+/- 5%, +/- 10%)
- +3.3V (+/- 5%, +/- 10%)
- +3.0V (+/- 10%)
s Active low reset, CAT1640
s Active high reset, CAT1641
s Valid reset guaranteed at V_CC=1V
s 400kHz I²C bus
s 3.0V to 5.5V operation
s Low power CMOS technology
s 64-Byte page write buffer
s 1,000,000 Program/Erase cycles
s 100 year data retention
s 8-pin DIP, SOIC, TSSOP and TDFN packages
s Industrial temperature range
DESCRIPTION
The CAT1640 and CAT1641 are complete memory and
supervisory solutions for microcontroller-based systems.
A 64kbit serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together in low power CMOS technology. Memory
interface is via a 400kHz I²C bus.
The CAT1640 provides a precision V_CC sense circuit
and drives an open drain output, RESET low whenever
V_CC falls below the reset threshold voltage.
The CAT1641 provides a precision VCC sense circuit
that drives an open drain output, RESET high whenever
VCC falls below the reset threshold voltage.
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals become
active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive
typically 200 ms after the supply voltage exceeds the reset
threshold level. With both active high and low reset options,
interface to microcontrollers and other ICs is simple. In
addition, the RESET (CAT1640) pin can be used as an
input for push-button manual reset capability.
The CAT1640/41 memory features a 64-byte page. In
addition, hardware data protection is provided by a VCC
sense circuit that prevents writes to memory whenever VCC
falls below the reset threshold or until VCC reaches the reset
threshold during power up.
Available packages include an 8-pin DIP, SOIC, TSSOP
and 4.9 x 3mm TDFN.
PIN CONFIGURATION
PDIP (L) SOIC (W)
A0 ¹
A1 2
A2 3
VSS 4
CAT1640
8 _VCC
7 RESET
6 SCL
5 SDA
A0 ¹
A1 2
A2 3
VSS 4
TSSOP (Y)
CAT1640
8 _VCC
7 RESET
6 SCL
5 SDA
TDFN PACKAGE: 4.9MM X 3MM
(ZD2)
A0 1
A1 2
A2 ³
VSS ⁴
CAT1640
8 VCC
7 _RESET
6 _SCL
5 _SDA
A0 1
A1 2
A2 3
VSS 4
CAT1641
8 _VCC
7 RESET
6 SCL
5 SDA
A0 1
A1 2
A2 3
VSS 4
CAT1641
8 _VCC
7 RESET
6 SCL
5 SDA
A0 1
A1 ²
A2 ³
VSS ⁴
CAT1641
8 VCC
7 RESET
6 _SCL
5 _SDA
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-3012, Rev. B