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28LV64 Datasheet, PDF (1/12 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL EEPROM | |||
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CAT28LV64
64K-Bit CMOS PARALLEL EEPROM
FEATURES
â 3.0V to 3.6 V Supply
â Read access times:
â 150/200/250ns
â Low power CMOS dissipation:
â Active: 8 mA max.
â Standby: 100 µA max.
â Simple write operation:
â On-chip address and data latches
â Self-timed write cycle with auto-clear
â Fast write cycle time:
â 5ms max.
â Commercial, industrial and automotive
temperature ranges
ALOGEN FR
LEA D F REETM
â CMOS and TTL compatible I/O
â Automatic page write operation:
â 1 to 32 bytes in 5ms
â Page load timer
â End of write detection:
â Toggle bit
â DATA polling
â Hardware and software write protection
â 100,000 program/erase cycles
â 100 year data retention
DESCRIPTION
The CAT28LV64 is a low voltage, low power, CMOS
parallel EEPROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and VCC power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bit signal the start and end of the self-
timed write cycle. Additionally, the CAT28LV64 features
hardware and software write protection.
The CAT28LV64 is manufactured using Catalystâs
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
BLOCK DIAGRAM
A5âA12
ADDR. BUFFER
& LATCHES
VCC
CE
OE
WE
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
A0âA4
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
8,192 x 8
E2PROM
ARRAY
32 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0âI/O7
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1010, Rev. D
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