CAT24WC32 Datasheet, PDF (7/8 Pages) Catalyst Semiconductor – 32K/64K-Bit I2C Serial CMOS E2PROM

Preliminary
CAT24WC32/64
memory location accessed is protected from program-
ming by the device’s failure to send an acknowledge
after the first byte of data is received.
READ OPERATIONS
The READ operation for the CAT24WC32/64 is initiated
in the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current Ad-
dress READ, Selective/Random READ and Sequential
READ.
Immediate/Current Address Read
The CAT24WC32/64’s address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. If N=E (where E=4095
for 24WC32 and E=8191 for 24WC64), then the counter
will ‘wrap around’ to address 0 and continue to clock out
data. After the CAT24WC32/64 receives its slave ad-
dress information (with the R/W bit set to one), it issues
an acknowledge, then transmits the 8 bit byte requested.
The master device does not send an acknowledge, but
will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi-
tion, slave address and byte addresses of the location it
wishes to read. After CAT24WC32/64 acknowledges,
the Master device sends the START condition and the
slave address again, this time with the R/W bit set to one.
The CAT24WC32/64 then responds with its acknowl-
edge and sends the 8-bit byte requested. The master
device does not send an acknowledge but will generate
a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24WC32/64 sends the initial 8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24WC32/64 will continue to output an 8-
bit byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24WC32/64 is
outputted sequentially with data from address N fol-
lowed by data from address N+1. The READ operation
address counter increments all of the CAT24WC32/64
address bits so that the entire memory array can be read
during one operation. If more than E (where E=4095 for
24WC32 and E=8191 for 24WC64) bytes are read out,
the counter will ‘wrap around’ and continue to clock out
data bytes.
Figure 8. Immediate Address Read Timing
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
S
T
DATA
O
P
SDA LINE S
P
A
N
C
O
K
A
C
K
SCL
8
9
SDA
8TH BIT
DATA OUT
NO ACK
STOP
24WC32/64 F10
7
Doc. No. 25053-00 2/98 S-1