CAT24WC01 Datasheet, PDF (7/9 Pages) Catalyst Semiconductor – 1K/2K/4K/8K/16K-Bit Serial E2PROM

CAT24WC01/02/04/08/16
the Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to P (P=7 for 24WC01 and P=15 for
CAT24WC02/04/08/16) additional bytes. After each byte
has been transmitted the CAT24WC01/02/04/08/16 will
respond with an acknowledge, and internally increment
the low order address bits by one. The high order bits
remain unchanged.
If the Master transmits more than P+1 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be overwrit-
ten.
Once all P+1 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24WC01/02/04/08/16 in a single write cycle.
Acknowledge Polling
The disabling of the inputs can be used to take advan-
tage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24WC01/02/04/08/16 initiates the
internal write cycle. ACK polling can be initiated imme-
diately. This involves issuing the start condition followed
by the slave address for a write operation. If the
CAT24WC01/02/04/08/16 is still busy with the write
operation, no ACK will be returned. If the CAT24WC01/
02/04/08/16 has completed the write operation, an ACK
will be returned and the host can then proceed with
thenext read or write operation.
Figure 6. Byte Write Timing
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24WC01/
02/04/08/16 will accept both slave and byte addresses,
but the memory location accessed is protected from
programming by the device’s failure to send an acknowl-
edge after the first byte of data is received.
READ OPERATIONS
The READ operation for the CAT24WC01/02/04/08/16
is initiated in the same manner as the write operation
with the one exception that the R/W bit is set to a one.
Three different READ operations are possible: Immedi-
ate Address READ, Selective READ and Sequential
READ.
Immediate Address Read
The CAT24WC01/02/04/08/16’s address counter con-
tains the address of the last byte accessed, incremented
by one. In other words, if the last READ or WRITE
access was to address N, the READ immediately follow-
ing would access data from address N+1. If N=E (where
E = 127 for 24WC01, 255 for 24WC02, 511 for 24WC04,
1023 for 24WC08, and 2047 for 24WC16), then the
counter will 'wrap around' to address 0 and continue to
S
T
BUS ACTIVITY: ^A
MASTER ^R
T
SDA LINE S
SLAVE
ADDRESS
BYTE
ADDRESS
*
S
T
DATA
O
P
P
A
A
A
C
C
C
K
K
K
5020 FHD F08
Figure 7. Page Write Timing
S
T
BUS ACTIVITY: ^A
SLAVE
MASTER ^R ADDRESS
T
SDA LINE S
BYTE
ADDRESS (n)
*
A
A
C
C
K
K
DATA n
DATA n+1
A
A
C
C
K
K
S
T
DATA n+P ^O
P
P
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
P=7 for CAT24WC01 and P=15 for CAT24WC02/04/08/16
* = Don't care for CAT24WC01
24WCXX F09
7
Doc. No. 25051-00 3/98 S-1