CAT24C321 Datasheet, PDF (10/12 Pages) Catalyst Semiconductor – Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer

CAT24C321/322/641/642
Advanced
Immediate/Current Address Read
The CAT24CXXX’s address counter contains the ad-
dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac-
cess data from address N+1. If N=E (where E=4095 for
24C321/322 and E=8191 for 24C641/642), then the
counter will ‘wrap around’ to address 0 and continue to
clock out data. After the CAT24CXXX receives its slave
address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an ac-
knowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi-
tion, slave address and byte addresses of the location it
wishes to read. After CAT24CXXX acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/W bit set to one.
The CAT24CXXX then responds with its acknowledge
and sends the 8-bit byte requested. The master device
does not send an acknowledge but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24CXXX sends the initial 8-bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24CXXX will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24CXXX is output-
ted sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24CXXX address bits
so that the entire memory array can be read during one
operation. If more than E (where E= 4095 for 24C321/
322, E=511 and E=8191 for 24C641/642) bytes are read
out, the counter will ‘wrap around’ and continue to clock
out data bytes.
Figure 10. Selective Read Timing
S
T
BUS ACTIVITY: ^A SLAVE
MASTER ^R ADDRESS
T
BYTE ADDRESS
A15–A8
A7–A0
S
T
A _SLAVE
R _ADDRESS
T
S
T
DATA
O
P
SDA LINE S
XXX *
S
P
A
A
A
C
C
C
K
K
K
* = Don't care bit for 24C321/322
A
N
C
O
K
A
C
K
X= Don't care bit
Figure 11. Sequential Read Timing
BUS ACTIVITY: SLAVE
MASTER ADDRESS
SDA LINE
A
C
K
DATA n
DATA n+1
DATA n+2
A
A
A
C
C
C
K
K
K
S
T
DATA n+x
O
P
P
N
O
A
C
K
Doc. No. 25083-00 12/98
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