SD310 Datasheet, PDF (2/3 Pages) Calogic, LLC – High-Speed Analog N-Channel DMOS FETs Improved On -Resistance

CORPORATION
SD310 / SD312 / SD314
ABSOLUTE MAXIMUM RATINGS
Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Total Device Dissipation at 25^oC Case Temperature . . . 1.2W
Storage Temperature Range . . . . . . . . . . . . . . -65^o to +200^oC
Lead Temperature (1/16" from case for 10 sec.). . . . . . 300^oC
Operating Temperature Range . . . . . . . . . . . -55^oC to +125^oC
PARAMETER
SD310 SD312 SD314
VDS Drain-to-source +30 +10 +20
VSD Source-to-drain* +10 +10 +20
VDB Drain-to-body +30 +15 +25
VSB Source-to-body +15 +15 +25
VGS Gate-to-source ±40 ±40 ±40
VGB Gate-to-body
±40 ±40 ±40
VGD Gate-to-drain
±40 ±40 ±40
UNIT
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
DC ELECTRICAL CHARACTERISTICS (TA = 25^oC, unless other specified.)
SYMBOL
PARAMETER
BREAKDOWN VOLTAGE
BVDS
Drain-to-source
BVSD
Source-to drain
BVDB
Drain-to-body
BVSB
Source-to-body
LEAKAGE CURRENT
IDS (OFF) Drain-to-source
ISD (OFF) Source-to-drain
IGBS
Gate
VT
Threshold voltage
rDS (ON)
Drain-to-source
resistance
SD310
SD312
SD314
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
TEST CONDITIONS
30 35
10 25
10
15
15
10 25
10
15
15
20 25
20
25
25
VGS = VBS = 0V, ID = 10µA
VGS = VBS = -5V, IS = 10nA
V
VGD = VBD = -5V, ID = 10nA
VGB = 0V, source OPEN, ID = 10nA
VGB = 0V, drain OPEN, IS = 10µA
1 10
1 10
VGS = VBS = -5V, VDS = +10V
1 10
1 10
1 10
VGS = VBS = -5V, VDS = +20V
nA _{VGS = VBD = -5V, VSD = +10V}
1 10
VGS = VBD = -5V, VSD = +20V
0.1
0.1
0.1
VDB = VSB = 0V, VGS = ±40V
0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 V VDS = VGS = VT, IS = 1µA, VSB = 0V
30 50
20 35
30 50
20 35
30 50
20 35
ID = 1.0mA, VSB = 0, VGS = +5V
Ω _{ID = 1.0mA, VSB = 0, VGS = +10V}
15 25
15
15
ID = 1.0mA, VSB = 0, VGS = +15V
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
SD310
SD312
SD314
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
TEST CONDITIONS
gfs
Forward
transconductance
15
20
15 20
15 20
mmhos
VDS = 10V, VSB = 0V, ID = 20mA,
f = 1kHz
SMALL SIGNAL CAPACITANCES (See capacitance model)
C(GS+GD+GB) Gate node
2.4 3.7
2.4 3.7
2.4 3.7
C(GD+DB)
C(GS+SB)
Drain node
Source node
1.3 1.7
3.5 4.5
1.3 1.7
3.5 4.5
1.3 1.7
pF
VDS = 10V, f = 1MHz
VGS = VBS = -15V
3.5 4.5
CDG
Reverse transfer
0.3 0.7
0.3 0.7
0.3 0.7