J108_15 Datasheet, PDF (1/1 Pages) Calogic, LLC – N-Channel JFET Switch

N-Channel JFET Switch
LLC
J108 – J110 / SST108 – SST110
FEATURES
Low Cost
• _{Automated Insertion Package}
• _{Low Insertion Loss}
•• _{No Offset or Error Voltages Generated by Closed Switch}
Purely Resistive
High Isolation Resistance from Driver
Fast Switching
•• _{Low Noise}
PIN CONFIGURATION
TO-92
D ^SG
5018
SOT-23
G
D
S
PRODUCT MARKING (SOT-23)
SST108
I08
SST109
I09
SST110
I10
APPLICATIONS
Analog Switches
• _Choppers
• _Commutators
•• _{Low-Noise Audio Amplifiers}
A_(TB_AS₌O₂L₅U_oCTE_unM_leA_sX_sIM_otU_heM_rwR_isA_eT_sIN_peG_cS_ified)
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . -25V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Storage Temperature Range . . . . . . . . . . . . . -55^oC to +150^oC
Operating Temperature Range . . . . . . . . . . . -55^oC to +135^oC
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300^oC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW
Derate above 25^oC . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/^oC
NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ORDERING INFORMATION
Part
Package
J108-110 Plastic TO-92
XJ108-110 Sorted Chips in Carriers
SST109-110 Plastic SOT-23
Temperature Range
-55^oC to +135^oC
-55^oC to +135^oC
-55^oC to +135^oC
ELECTRICAL CHARACTERISTICS (TA = 25^oC unless otherwise specified)
SYMBOL
IGSS
VGS(off)
BVGSS
IDSS
ID(off)
rDS(on)
Cdg(off)
Csg(off)
Cdg(on)
+ Csg(on)
td(on)
tr
td(off)
tf
PARAMETER
Gate Reverse Current (Note 1)
Gate-Source Cutoff Voltage
Gate-Source Breakdown Voltage
Drain Saturation Current (Note 2)
Drain Cutoff Current (Note 1)
Drain-Source ON Resistance
Drain-Gate OFF Capacitance
Source-Gate OFF Capacitance
Drain-Gate Plus Source-Gate
ON Capacitance
Turn On Delay Time
Rise Time
Turn OFF Delay Time
Fall Time
108
109
110
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
-3
-3
-3 nA
-3
-10 -2
-25
-25
-6 -0.5
-25
-4
V
80
40
10
mA
3
3
3 nA
8
12
18 Ω
15
15
15
15
15
15 _pF
85
85
85
4
4
4
1
1
1
6
6
6
ns
30
30
30
TEST CONDITIONS
VDS = 0V, VGS = -15V
VDS = 5V, ID = 1µA
VDS = 0V, IG = -1µA
VDS = 15V, VGS = 0V
VDS = 5V, VGS = -10V
VDS ≤0.1V, VGS = 0V
VDS = 0,
VGS = -10V
(Note 3)
f = 1MHz
VDS = VGS = 0
(Note 3)
Switching Time Test
Conditions (Note 3)
J107 J109
VDD 1.5V 1.5V
VGS(off) -12V -7V
RL 150Ω 150Ω
J110
1.5V
-5V
150Ω
NOTES: 1. Approximately doubles for every 10^oC increase in TA.
2. Pulse test duration = 300µs; duty cycle ≤3%.
3. For design reference only, not 100% tested.
CALOGIC LLC, 237 WHITNEY PLACE, FREMONT, CA 94539, 510-656-2900 PHONE, 510-651-1076 FAX
DS038 REV A