IT1750 Datasheet, PDF (1/1 Pages) Calogic, LLC – N-Channel Enhancement Mode MOSFET General Purpose Amplifier Switch

N-Channel
Enhancement Mode MOSFET
General Purpose Amplifier Switch
IT1750
CORPORATION
FEATURES
Low ON Resistance
• _{Low Cdg}
• _{High Gain}
•• _{Low Threshold Voltage}
PIN CONFIGURATION
TO-72
1003
D
G
C
S
ABSOLUTE MAXIMUM RATINGS
(TA = 25^oC unless otherwise specified)
Drain-Source and Gate-Source Voltage . . . . . . . . . . . . . . 25V
Peak Gate-Source Voltage (Note 1) . . . . . . . . . . . . . . . ±125V
Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Storage Temperature Range . . . . . . . . . . . . . -65^oC to +200^oC
Operating Temperature Range . . . . . . . . . . . -65^oC to +150^oC
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300^oC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375mW
Derate above 25^oC . . . . . . . . . . . . . . . . . . . . . . . . 3mW/^oC
NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ORDERING INFORMATION
Part
Package
IT1750 Hermetic TO-72
XIT1750 Sorted Chips in Carriers
Temperature Range
-55^oC to +150^oC
-55^oC to +150^oC
ELECTRICAL CHARACTERISTICS (TA = 25^oC, Body connected to Source and VBS = 0 unless otherwise specified)
SYMBOL
PARAMETER
VGS(th)
Gate to Source Threshold Voltage
MIN
0.50
MAX
3.0
UNITS
V
TEST CONDITIONS
VDS = VGS, ID = 10µA
IDSS
Drain Leakage Current
10
nA
VDS = 10V, VGS = 0
IGSS
Gate Leakage Current
(See note 2)
BVDSS
Drain Breakdown Voltage
25
V
ID = 10µA, VGS = 0
rDS(on)
Drain to Source on Resistance
50
ohms VGS = 20V
ID(on)
Drain Current
10
mA
VDS = VGS =10V
Yfs
Forward Transadmittance
3,000
µS
VDS = 10V, ID = 10mA, f = 1kHz
Ciss
Total Gate Input Capacitance
6.0
pF
ID = 10mA, VDS = 10V, f = 1MHz (Note 3)
Cdg
Gate to Drain Capacitance
1.6
pF
VDG = 10V, f = 1MHz (Note 3)
NOTES: 1. Devices must not be tested at ±125V more than once nor longer than 300ms.
2. Actual gate current is immeasurable. Package suppliers are required to guarantee a package leakage of < 10pA.
External package leakage is the dominant mode which is sensitive to both transient and storage environment, which cannot be guaranteed.
3. For design reference only, not 100% tested.