PACDN009 Datasheet, PDF (6/8 Pages) California Micro Devices Corp – 5 Channel ESD Protection Array

PACDN009
Application Information (cont’d)
Implementation Examples
ESD events are very high-speed pulses with rise times
in the range of 1ns or less. To effectively use the
PACDN009, the following design guidelines must be
observed (as discussed in the application section):
1) The inductance from the V_N and V_P connections of
the PACDN009 to ground must be very low. This
includes the path through the V_P decoupling capacitor
to ground and the path to the power supply (as dis-
cussed above).
2) The inductance between the connector pin to be
protected and the PACDN009 channel input pin must
be kept to a minimum. If there is a large inductance
here, the ESD event will find a lower impedance path
which will more likely be through the device to be pro-
tected. Figure 2 shows the implementation schematic
and Figure 3 shows a possible layout for the
PACDN009. In figure 3, notice the large VCC and
ground areas with multiple via connections to the
underlying reference planes and the positioning of the
bypass capacitor. Note how the signal lines to be pro-
tected flow from the connector to the PACDN009 and
then out to the device to be protected (Figure 3). This
daisy chaining provides a low impedance path from the
connector to the PACDN009 and a higher impedance
path from the PACDN009 to the protected device.
POSITIVE SUPPLY RAIL
CHANNEL
INPUT
D₁
ONE
D₂
CHANNEL
OF
PAC DN009
DECOUPLING
CAPCITOR
0.22µF
LINE BEING
PROTECTED
OPTIONAL
ZENER DIODE
FOR EXTRA
PROTECTION
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
GROUND RAIL
Figure 2. Typical ESD protection implementation
POWER SUPPLY
© 2004 California Micro Devices Corp. All rights reserved.
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