PACVGA105 Datasheet, PDF (4/6 Pages) California Micro Devices Corp – VGA Port Companion Circuit

PACVGA105
Specifications (cont’d)
ELECTRICAL OPERATING CHARACTERISTICS ^{(SEE NOTE 1)}
SYMBOL PARAMETER
V_F
Diode Forward Voltage
V_OH Logic High Output Voltage
V_OL Logic Low Output Voltage
I_IN
Input Current
R, G and B pins
HSYNC, VSYNC pins
HSYNC, VSYNC pins
I_CC
V_CC Supply Current
I_RGB V_RGB Supply Current
C_IN
R_PU
V_ESD
Input Capacitance
R, G and B pins
HSYNC, VSYNC pins
DDC_DATA, DDC_CLK pins
Pull-up Resistance
DDC_DATA, DDC_CLK pins
ESD Withstand Voltage
t_PLH
t_PHL
t_R, t_F
SYNC Buffer L => H
Propagation Delay
SYNC Buffer H => L
Propagation Delay
SYNC Buffer Output Rise & Fall
Times
CONDITIONS
I_F = 10mA
I_OH = -4mA, V_CC = 4.5V
I_OL = 4mA, V_CC = 4.5V
V_RGB = 3.63V, V_IN = V_RGB or GND
V_AUX = 3.63V, V_IN = V_AUX
V_AUX = 3.63V, V_IN = GND
V_CC = 5.5V; V_AUX = V_RGB = 2.97V; All
inputs and outputs floating
R, G and B pins at V_CC or GND; All
inputs and outputs floating
Note 2 applies for all cases
V_CC = 5V; V_RGB = 3.3V;
V_AUX = 3.3V; Note 3
C_L = 50pF; V_CC = 5.0V;
R_L = 500Ω; Note 4
C_L = 50pF; V_CC = 5.0V;
R_L = 500Ω; Note 4
C_L = 50pF; V_CC = 5.0V;
R_L = 500Ω; Note 4
MIN TYP MAX UNITS
1.0
V
4.0
V
0.4
V
+1
µA
+1
µA
-30 -72.5 -95
µA
35
100
µA
10
µA
5
pF
10
pF
5
pF
1.62 1.8 1.98 kΩ
±8
kV
7.0 15.0 ns
7.0 15.0 ns
7.0
ns
Note 1: All parameters specified over standard operating conditions unless otherwise noted.
Note 2: Measured at 1MHz. R/G/B inputs biased at 1.65V with V_RGB = 3.3V. DDC_CLK and DDC_DATA biased at 2.5V with
V_CC=5V. HSYNC and VSYNC inputs biased at V_AUX or GND with V_AUX = 3.3V and V_CC = 5V. These parameters are guaran-
teed by design and characterization
Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. V_RGB and V_CC must be bypassed to
GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse
is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable
pins are: R, G, B, HSYNC_OUT, VSYNC_OUT, DDC_CLK and DDC_DATA. The HSYNC and VSYNC inputs are ESD pro-
tected to the industry standard 2kV per the Human Body Model (MIL-STD-883, Method 3015).
Note 4: Applicable to the SYNC buffers only. Input signals swing between 0V and 3.0V, with rise and fall times ≤ 5ns. Guaranteed by
correlation to buffer output drive currents.
© 2004 California Micro Devices Corp. All rights reserved.
4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: [phone]
L Fax: [phone] L www.calmicro.com
01/28/04