CM2031 Datasheet, PDF (4/14 Pages) California Micro Devices Corp – HDMI Receiver Port Protection and Interface Device

Issue X-1
CM2031
Backdrive Protection and Isolation
Backdrive current is defined as the undesirable current
flow through an I/O pin when that I/O pin’s voltage
exceeds the related local supply voltage for that
circuitry. This is a potentially common occurrence in
multimedia entertainment systems with multiple
components and several power plane domains in each
system.
For example, if a DVD player is switched off and an
HDMI connected TV is powered on, there is a
possibility of reverse current flow back into the main
power supply rail of the DVD player from pull-ups in the
TV. As little as a few milliamps of backdrive current
flowing back into the power rail can charge the DVD
player’s bulk bypass capacitance on the power rail to
some intermediate level. If this level rises above the
power-on-reset (POR) voltage level of some of the
integrated circuits in the DVD player, then these
devices may not reset properly when the DVD player is
turned back on.
If any SOC devices are incorporated in the design
which have built-in level shifter and/or ESD protection
structures, there can be a risk of permanent damage
due to backdrive. In this case, backdrive current can
forward bias the on-chip ESD protection structure. If
the current flow is high enough, even as little as a few
milliamps, it could destroy one of the SOC chip’s
internal DRC diodes, as they are not designed for
passing DC.
To avoid either of these situations, the CM2031 was
designed to block backdrive current, guaranteeing less
than 5μA into any I/O pin when the I/O pin voltage
exceeds its related operating CM2031 supply voltage.
LOW VOLTAGE
HDMI ASIC
LV_SUPPLY
=OFF
+5V
ASIC
LV_SUPPLY
=OFF
LOW VOLTAGE
HDMI ASIC
+5V
ASIC
HDMISOURCE
HDMISINK
HDMI SOURCE
HDMI SINK
Figure 1. Backdrive Protection Diagram.
Display Data Channel (DDC) lines
The DDC interface is based on the I²C serial bus
protocol for EDID configuration.
DYNAMIC PULLUPS
Based on the HDMI specification, the maximum
capacitance of the DDC line can approach 800pF
(50pF from source, 50pF from sink, and 700pF from
cable). At the upper range of capacitance values (i.e.
long cables), it becomes impossible for the DDC lines
to meet the I²C timing specifications with the minimum
pull-up resistor of 1.5k Ω (at the source).
For this reason, the CM2031 was designed with an
internal I²C accelerator to meet the AC timing
specification even with very long and non-compliant
cables.
The internal accelerator works with the source pull-up
and the local 47kΩ pullup to increase the positive slew
rate of the DDC_CLK_OUT and DDC_DAT_OUT lines
whenever the sensed voltage level exceeds
0.3*5V_SUPPLY (approximately 1.5V). This provides
faster overall risetime in heavily loaded situations
without overloading the mutli-drop open drain I²C
outputs elsewhere.
© 2007 California Micro Devices Corp. All rights reserved.
4
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