PACSZ1284_06 Datasheet, PDF (3/7 Pages) California Micro Devices Corp – IEEE 1284 Parallel Port ESD/EMI/Termination Network

PACSZ1284
Specifications
PARAMETER
V_CC Voltage
Input Voltage Range, no clamping
Storage Temperature Range
Power Dissipation per Resistor
Package Power Dissipation
ABSOLUTE MAXIMUM RATINGS
RATING
5.5
-0.4 to 5.5
-40 to +150
0.1
1.0
UNITS
V
V
°C
W
W
PARAMETER
V_CC Voltage
Operating Temperature
STANDARD OPERATING CONDITIONS
RATING
5.0
-40 to +85
UNITS
V
°C
ELECTRICAL OPERATING CHARACTERISTICS
SYMBOL PARAMETER
CONDITIONS
MIN
TOL_R Absolute Resistance Tolerance
Measured at T_A=25°C
TOL_C
Absolute Capacitance Tolerance
Measured at 1MHz, 2.5VDC,
T_A=25°C
I_LEAK Leakage current to GND
Measured at 5.0VDC, T_A=25°C
V_ESDi ESD protection, input pins
Pins 3,4,5,6,7,9,11,13, & 14, per IEC
+8
61000-4-2 specification,
Notes 1,2,3
V_ESD ESD protection, connector pins
Pins 1,2,8,10,12,15,16,17,18,19,
+30
21,23,24,25,26,27, & 28, per
IEC 61000-4-2 specification
Notes 1,2,4
V_CLAMP Clamping voltage under ESD
discharge
ESD applied to connector pin, mea-
sured at corresponding input pin;
+8kV discharge, Human Body Model
Notes 1,2
ESD applied to connector pin,
measured at corresponding input pin;
-8kV discharge, Human Body Model;
Notes 1,2
Note 1: Guaranteed by design and characterization.
Note 2: ESD voltage applied between Input/Connector pins and ground, one pin at a time.
Note 3: Pins 3-7, 9, 11, 13, and 14 typically connect to the I/O pins of a Super I/O chip.
Note 4: Pins 1, 2, 8, 10, 12, 15-19, 21, and 23-28 typically connect to the Parallel Port connector.
TYP
1
8.3
-2.7
MAX
+20
+20
UNITS
%
%
10
μA
kV
kV
V
V
© 2006 California Micro Devices Corp. All rights reserved.
06/28/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: [phone] ● Fax: [phone] ● www.cmd.com 3