PACDN016 Datasheet, PDF (3/3 Pages) California Micro Devices Corp – 6 CHANNEL ESD PROTECTION ARRAY WITH ZENER SUPPLY CLAMP

CALIFORNIA MICRO DEVICES
PAC DN016
Similarly for negative ESD pulses, parasitic series inductance from the V_N pin to the ground rail will lead to drastically increased
negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit a
much higher output impedance to fast transient current spikes. In the V_Z equation above, the V_Supply term, in reality, is given
by (V_DC + I_esd x R_out), where V_DC and R_out are the nominal supply DC output voltage and effective output impedance of the
power supply respectively. As an example, a R_out of 1 ohm would result in a 10V increment in V_Z for a peak I_esd of 10A.
To mitigate these effects, a Zener diode has been integrated into this Protection Array between V_P and V_N. This Zener diode
clamps the maximum voltage of V_P relative to V_N at the breakdown voltage of the Zener diode. Although not strictly necessary,
it is recommended that V_P be bypassed to the ground plane with a high frequency bypass capacitor. This will lower the
channel clamp voltage, and is especially effective when V_P is much lower than the Zener breakdown voltage. The value of this
bypass capacitor should be chosen such that it will absorb the charge transferred by the ESD pulse with minimal change in V_P.
Typically a value in the 0.1 µF to 0.2 µF range is adequate for IEC-61000-4-2 level 4 contact discharge protection (8KV). For
higher ESD voltages, the bypass capacitor should be increased accordingly. Ceramic chip capacitors mounted with short
printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have poor
high frequency characteristics.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic
discharges. The power supply bypass capacitor mentioned above should be as close to the V_P pin of the Protection Array as
possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray series inductance.
Figure 5
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