PACDN006 Datasheet, PDF (3/3 Pages) California Micro Devices Corp – 6 CHANNEL ESD PROTECTION ARRAY

CALIFORNIA MICRO DEVICES
PACDN006
Application Information
See also California Micro Devices Application note
AP209, “Design Considerations for ESD protection.”
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances to the Supply
and Ground rails. Refer to Figure 1, which illustrates
the case of a positive ESD pulse applied between an
input channel and Chassis Ground. The parasitic
series inductance back to the power supply is repre-
sented by L₁. The voltage V_Z on the line being pro-
tected is:
V_Z = Forward voltage drop of D₁ + L₁ x d(I_ESD)/
dt + V_SUPPLY
where I_ESD is the ESD current pulse, and
V_SUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC 61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1nS. Here d(I_ESD)/dt can be approximated by
DI /Dt, or 30/(1x10^-9). So just 10nH of series induc-
ESD
tance (L₁) will lead to a 300V increment in V_Z!
Similarly for negative ESD pulses, parasitic series
inductance from the V_N pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
Another consideration is the output impedance of the
power supply for fast transient currents. Most power
supplies exhibit a much higher output impedance to
fast transient current spikes. In the V_Z equation above,
the V
term, in reality, is given by (V + I x
SUPPLY
DC
ESD
R_OUT), where V_DC and R_OUT are the nominal supply DC
output voltage and effective output impedance of the
power supply respectively. As an example, a R_OUT of 1
ohm would result in a 10V increment in V_Z for a peak
I_ESD of 10A.
To mitigate these effects, a high frequency bypass
capacitor should be connected between the V_P pin of
the ESD Protection Array and the ground plane. The
value of this bypass capacitor should be chosen such
that it will absorb the charge transferred by the ESD
pulse with minimal change in V_P. Typically a value in
the 0.1µF to 0.2µF range is adequate for
IEC-61000-4-2 level 4 contact discharge protection
(8KV). For higher ESD voltages, the bypass capacitor
should be increased accordingly. Ceramic chip capaci-
tors mounted with short printed circuit board traces are
good choices for this application. Electrolytic capaci-
tors should be avoided as they have poor high fre-
quency characteristics. For extra protection, connect a
zener diode in parallel with the bypass capacitor to
mitigate the effects of the parasitic series inductance
inherent in the capacitor. The breakdown voltage of the
zener diode should be slightly higher than the maxi-
mum supply voltage.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the V_P pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply and
ground planes to minimize stray series inductance.
Figure 1.
©2000 California Micro Devices Corp. All rights reserved. All rights reserved. PAC DN006™ is a tradmark of California Micro Devices Corp.
6/19/2000
215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com
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