PACDN007 Datasheet, PDF (2/3 Pages) California Micro Devices Corp – 18 CHANNEL ESD PROTECTION ARRAY

CALIFORNIA MICRO DEVICES
Input Capacitance vs. Input Voltage
PAC DN007
V_IN
Typical variation of C_IN with V_IN
(V_P = 5V, V_N = 0V, 0.1µF chip capacitor between V_P & V_N)
STANDARD PART ORDERING INFORMATION
Package
Ordering Part Number
Pins
Style
Part Marking
24
QSOP
PACDN007Q
When placing an order please specify desired shipping: Tubes or Tape & Reel.
Application Information
See also California Micro Devices Application note AP209, “Design Considerations for ESD protection.”
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive ESD pulse
applied between an input channel and Chassis Ground. The parasitic series inductance back to the power supply is
represented by L₁. The voltage V_Z on the line being protected is:
V_Z = Forward voltage drop of D₁ + L₁ x d(I_esd)/dt + V_Supply
where I_esd is the ESD current pulse, and V_Supply is the positive supply voltage.
Figure 1
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per
the IEC 61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1nS. Here d(I_esd)/dt can be
approximated by ∆I_esd/∆t, or 30/(1x10^-9). So just 10nH of series inductance (L₁) will lead to a 300V increment in V_Z!
© 1999 California Micro Devices Corp. All rights reserved.
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