CM4072 Datasheet, PDF (2/11 Pages) California Micro Devices Corp – Low Noise Charge Pump/Linear Regulator LED Driver

PRELIMINARY
CM4072
PACKAGE / PINOUT DIAGRAM
TOP VIEW
(Pins Down View)
10 9 8 7 6
BOTTOM VIEW
(Pins Up View)
1 23 45
Pin 1
Marking
Note: This drawing is not to scale.
CM407
GND
250xx
PAD
1 23 45
10 9 8 7 6
CM4072-50DF/DE
10 Lead TDFN Package
LEAD(S)
1
2
3
4
5
6, 7
NAME
DGND
V_IN
V_CP
GND
BYP
EN_LDO,
EN_CP
PIN DESCRIPTIONS
DESCRIPTION
Ground for the charge pump circuit. This should be connected to the system (noisy) ground.
Input power source for the device. Since the charge pump draws current in pulses at the
250kHz internal clock frequency, a low-ESR input decoupling capacitor is usually required close
to this pin to ensure low noise operation.
Charge pump output which is connected to the external reservoir capacitor C_S. This should be a
low-ESR capacitor. When the voltage on this pin reaches about 5.8V then the charge pump
pauses until the voltage on this pin drops to about 5.7V. This gives rise to at least 100mV of 'rip-
ple' (the frequency and amplitude of this ripple depends upon values of C_P and C_S and also the
ESR of C_S).
Ground reference for all internal circuits except the charge pump. This pin should be connected
to a "clean" low-noise analog ground
Bypass input connected to the internal voltage reference of the LDO regulator. An external
bypass capacitor C_BYP of 0.1uF is recommended to minimize internal voltage reference noise
and maximize power supply ripple rejection.
EN_LDO (pin 6) and EN_CP (pin 7) are active-high TTL-level logic inputs to enable the linear
regulator and charge pump according to the following truth table:
EN_CP
(Pin 7)
1
1
0
0
EN_LDO
(Pin 6)
1
0
1
0
CHARGE PUMP
Enabled
Enabled
Disabled
Disabled
REGULATOR
Enabled
Disabled
Disabled
Disabled
8
9, 10
V_OUT
CP+, CP-
The regulated output. An output capacitor may be added to improve noise and load-transient
response. When the LDO regulator is disabled, an internal pull-down with a nominal resistance
of 50 ohms is activated to discharge the V_OUT rail to GND
CP+ (pin 9) and CP- (pin 10) are used to connect the external "flying" capacitor C_P to the charge
pump. The charge stored in C_P is transferred to the reservoir capacitor C_S at the 250kHz inter-
nal clock rate.
© 2005 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: [phone] ● Fax: [phone] ● www.cmd.com 11/08/05