CM3004 Datasheet, PDF (2/9 Pages) California Micro Devices Corp – 1.0 Amp Dual Mode Low-Dropout CMOS Regulator

PACKAGE / PINOUT DIAGRAM
TOP VIEW
EN
IN
OUT
ADJ
1
8
2
7
3
6
4
5
GND
GND
GND
GND
Note: This drawing is not to scale.
8-Lead Power SOIC
PRELIMINARY
CM3004
LEAD(S)
1
2
3
4
5-8
NAME
EN
IN
OUT
ADJ
GND
PIN DESCRIPTIONS
DESCRIPTION
Enable/shutdown input. When EN is asserted high (V_EN ≥ 1.2V), the regulator is enabled. When EN
is asserted low (V_EN ≤ 0.4V), the regulator is shut down.
Positive input voltage for the regulator. If this input pin is greater than 2 inches from the main input
filter, a 10µF ceramic capacitor is recommended for adequate filtering.
The regulated voltage output. An output capacitor of 10µF is recommended to minimize any tran-
sient load disturbances under normal operating conditions. Additional output capacitance can be
used to further improve transient load response.
Feedback input. When ADJ is grounded, the device enters fixed voltage mode. When ADJ is con-
nected to an external resistor network, the device operates as an adjustable regulator. The Adjust
pin can also be tied directly to the OUT pin which configures the CM3004 as a 1.2V regulator.
The negative reference for all voltages. Also functions as a thermal path for heat dissipation.
Ordering Information
PART NUMBERING INFORMATION
Leads
8
Package
SOIC-8
Standard Finish
Ordering Part
Number¹
Part Marking
CM3004-25SA
CM3004 25SA
Lead-free Finish
Ordering Part
Number¹
Part Marking
CM3004-25SF
CM3004 25SF
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
© 2004 California Micro Devices Corp. All rights reserved.
2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: [phone] ● Fax: [phone] ● www.calmicro.com 01/10/05