SUPER1284 Datasheet, PDF (1/5 Pages) California Micro Devices Corp – P/ACTIVE IEEE 1284 ECP/EPP TERMINATION NETWORK

CCAALILFIOFORRNNIAIAMMICICRROODDEVEVICICESES
SUPER 1284
P/ACTIVE™ IEEE 1284 ECP/EPP TERMINATION NETWORK
Features
• Single chip IEEE 1284 parallel port termination
• 28 pin QSOP package, smallest physical solution
• 17 terminating lines in a single package
• In system ESD protection to 8KV, HBM
• In system ESD protection to 4KV per IEC1000-4-2
• Protects downstream devices to 30V
Applications
• ECP/EPP Parallel Port termination
• PC Peripherals
• Notebook and Desktop computers
• Engineering Workstations and Servers
Product Description
California Micro Devices’ Super 1284 Parallel Port Termination Network provides a complete integrated solution for the entire
IEEE 1284 interface in a single QSOP package.
Advanced, enhanced high-speed parallel ports, conforming to the IEEE 1284 standard, are used to provide communications
with external devices such as tape back-up drives, ZIP drives, printers, parallel port SCSI adapters, external LAN adapters, scanners,
video capture, and other PC peripherals. These advanced ports support bi-directional transfers to 2MB/sec. To effectively support
these higher transfer data rates, the IEEE 1284 standard recommends a combined termination, pull-up filter network between
the driver/receiver and the cable at both ends of the parallel port interface. In addition, government EMC compatibility
requirements impose strict filtering on the parallel port. California Micro Devices’ Super 1284 Parallel Port Termination Network
addresses all of these requirements by providing a seventeen line, IEEE 1284 compliant network in a thin film integrated circuit.
The device provides a complete parallel port termination solution for space critical applications by integrating a total of 43
discrete components. In addition, all I/O pins are ESD protected for contact discharges up to 4KV per the Human Body Model.
However, the output pins of the device which have the highest probability of exposure to ESD pulses are protected to 8KV, HBM,
thereby providing the necessary robustness for the port’s application environment.
California Micro Devices’ P/Active technology provides high reliability and low cost through manufacturing efficiency. The resistors
and capacitors are fabricated using proprietary state-of-the-art thin film technology. California Micro Devices’ solution is silicon-
based and has the same reliability characteristics as today’s integrated circuits.
STANDARD SPECIFICATIONS
Absolute Tolerance (R)
±10%
Absolute Tolerance (C)
±20%
Operating Temperature Range
0^oC to 70^oC
VCC
6V max
Power Rating/Resistor
100mW
Maximum Leakage Current
(at VCC Max)
1µA@25^oC
Signal Clamp Voltage:
Positive Clamp
>6V
Negative Clamp
<-6V
Storage Temperature
-65^oC to +150^oC
Package Power Rating
1.00W, max.
R1(W)
2.2K
4.7K
STANDARD VALUES
R2(W)
C(pF)
RC Code
33
220
02
33
180
04
SCHEMATIC CONFIGURATION
GND
V_CC
28
27 26
25
24
23 22 21 20
19
18
17
16
15
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1 R1
R1 R1
R1 R1
R1
R1
R2
R2
R2
R2
R2
R2
R2
R2
R2
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
1
2
3
4
5
6
78
9 10
11 12
13
14
©1998 California Micro Devices Corp. All rights reserved.
© 1998 California MP/iAcrcotivDee^®viicseas Creogrips.teArelldritgrahdtsemreaserkrvaendd. PAC is a trademark of California Micro Devices.
7/98 Rev. 1 7/98 Rev. 1 _{21521T5opTaozpSatzreSettr,eMet,ilpMitialpsi,taCsa, lCifoarlinfoiarni9a509355035 Tel:Te(l4: 0(84)0286) 32-6332-134214}
FaxF:a(x4: 0(84)0286) 32-6738-476846
www.wcwal.mcaiclmroic.crom.com
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