PACVGA203 Datasheet, PDF (1/8 Pages) California Micro Devices Corp – VGA Port Companion Circuit

PACVGA203
VGA Port Companion Circuit
Features
• Single-chip solution for the VGA port interface
• Includes ESD protection, level shifting, and RGB
termination
• Seven channels of ESD protection for all VGA port
connector pins, meeting IEC-61000-4-2 Level-4
ESD requirements (8kV contact discharge)
• Very low loading capacitance from ESD protection
diodes on VIDEO lines; 4pF typical
• 75Ω termination resistors for VIDEO lines
(matched to 1% typ.)
• TTL to CMOS level-translating buffers with power-
down mode for HSYNC and VSYNC lines
• Bi-directional level shifting N-channel FETs pro-
vided for DDC_CLK & DDC_DATA channels
• Compact 24-pin QSOP package
• Lead-free version available
Applications
• Notebook computers with VGA port
• Desktop PCs with VGA port
Product Description
The PACVGA203 incorporates seven channels of ESD
protection for all signal lines commonly found in a VGA
port. ESD protection is implemented with current
steering diodes designed to safely handle the high
surge currents encountered with IEC-61000-4-2 Level-
4 ESD Protection (8kV contact discharge). When a
channel is subjected to an electrostatic discharge, the
ESD current pulse is diverted via the protection diodes
into either the positive supply rail or ground where it
may be safely dissipated. Separate positive supply
rails are provided for the VIDEO, DDC and SYNC
channels to facilitate interfacing with low voltage Video
Controller ICs and provide design flexibility in multi-
supply-voltage environments.
Two non-inverting drivers provide buffering for the
HSYNC and VSYNC signals from the Video Controller
IC (SYNC_IN1, SYNC_IN2). These buffers accept TTL
input levels and convert them to CMOS output levels
that swing between Ground and V_CC4 (cont’d next
page).
Simplified Electrical Schematic
VIDEO_1 ³
VIDEO_2 ⁴
VIDEO_3 ⁵
GNDD ⁶
TERM_1 ⁸
TERM_2 ⁹
TERM_3 ¹⁰
GNDA ⁷
V_CC1
2
GNDD
75
75
75
GNDD
V_CC2
12
R_C
V_CC3
14
DDC_IN1 ¹⁶
15 _{DDC_OUT1}
GNDD
R_B
V_BIAS
D1
13
SYNC_IN1 ¹⁹
GNDD
V_CC2
GNDD
V_CC3
R_C
GNDD
DDC_IN2 ¹⁷
GNDD
18 _{DDC_OUT2}
SYNC_IN2 ²¹
V_CC4
1
V_CC4
1
20 _{SYNC_OUT1}
R_S
23 _SD1
GNDD
GNDD
11 _{PWR_UP}
R_C
GNDD
22
R_S
SYNC_OUT2
24 _SD2
GNDA
GNDD
GNDD
GNDD
© 2004 California Micro Devices Corp. All rights reserved.
12/07/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: [phone] ● Fax: [phone] ● www.calmicro.com 1