SPT7840 Datasheet, PDF (9/12 Pages) Fairchild Semiconductor – 10-BIT, 10 MSPS, 100 mW A/D CONVERTER

Typically, the top side voltage drop for V_RHF to V_RHS will
equal:
V_RHF – V_RHS = 2.25 % of (V_RHF – V_RLF) (typical),
and the bottom side voltage drop for V_RLS to V_RLF will
equal:
V_RLS – V_RLF = 1.9 % of (V_RHF – V_RLF) (typical).
Figure 4 shows an example of expected voltage drops for
a specific case. V_REF of 4.0 V is applied to V_RHF, and V_RLF
is tied to AGND. A 90 mV drop is seen at V_RHS (= 3.91 V),
and a 75 mV increase is seen at V_RLS (= 0.075 V).
ANALOG INPUT
V_IN is the analog input. The input voltage range is from
V_RLS to V_RHS (typically 4.0 V) and will scale proportionally
with respect to the voltage reference. (See voltage refer-
ence section.)
The drive requirements for the analog inputs are very
minimal when compared to most other converters due to
the SPT7840’s extremely low input capacitance of only
5 pF and very high input resistance of 50 kΩ.
The analog input should be protected through a series
resistor and diode clamping circuit as shown in figure 5.
Upon powerup, the SPT7840 begins its calibration algo-
rithm. In order to achieve the calibration accuracy re-
quired, the offset and gain adjustment step size is a frac-
tion of a 10-bit LSB. Since the calibration algorithm is an
oversampling process, a minimum of 10,000 clock cycles
are required. This results in a minimum calibration time
upon powerup of 500 µsec for a 10 MHz sample rate.
Once calibrated, the SPT7840 remains calibrated over
time and temperature.
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for the
SPT7840 to remain in calibration.
INPUT PROTECTION
All I/O pads are protected with an on-chip protection
circuit shown in figure 6. This circuit provides ESD robust-
ness to 3.5 kV and prevents latch-up under severe dis-
charge conditions without degrading analog transition
times.
Figure 6 – On-Chip Protection Circuit
V_DD
120 W
Analog
Figure 5 – Recommended Input Protection Circuit
+V
AV_DD
Pad
120 W
D1
Buffer
47 W
D2
ADC
–V
D1 = D2 = Hewlett-Packard HP5712 or equivalent
POWER SUPPLY SEQUENCING CONSIDERATIONS
All logic inputs should be held low until power to the device
has settled to the specific tolerances. Avoid power decou-
pling networks with large time constants that could delay
V_DD power to the device.
CALIBRATION
The SPT7840 uses an auto-calibration scheme to ensure
10-bit accuracy over time and temperature. Gain and off-
set errors are continually adjusted to 10-bit accuracy
during device operation. This process is completely trans-
parent to the user.
CLOCK INPUT
The SPT7840 is driven from a single-ended TTL-input
clock. Because the pipelined architecture operates on the
rising edge of the clock input, the device can operate over
a wide range of input clock duty cycles without degrading
the dynamic performance. The device’s sample rate is
1/2 of the input clock frequency. (See figure 1A timing
diagram.)
SPT7840
9
6/27/01