SPT7864 Datasheet, PDF (6/8 Pages) Cadeka Microcircuits LLC. – 10-BIT, 40 MSPS A/D CONVERTER

DIFFERENTIAL CLOCK INPUT
The SPT7864 clock can be driven differentially or single-
ended. When driven differentially, CLK and CLK accommo-
date differential sinusodial signals centered around V_DD/2.
The peak-to-peak value should be 0.8 V. In order to pre-
serve accuracy at high input frequency, it is important that
the clock have low jitter. The differential clock input is made
to allow a low-jitter clock design. To ensure low jitter, the
differential input should be a pure sine wave with low white
noise floor.
SINGLE-ENDED CLOCK INPUT
For single-ended operation, the CLK node is internally
biased to 1.5 V, and should externally be decoupled to
ground by a capacitor. A CMOS logic level clock (5 V or
3 V) is applied at the CLK node. (To get an inverted clock
input, CLK should be decoupled and the clock signal ap-
plied at the CLK node). The duty cycle of the clock should
be close to 50%. Consecutive pipeline stages in the ADC
are clocked in antiphase. With a 50% duty cycle, every
stage has the same time for settling. If the duty cycle devi-
Figure 3 – Driving Differential Inputs with a
Differential Configuration
V_IHD
V_ICM
V_ID
V_ILD
Figure 4 – Driving Differential Inputs with a
Single-Ended Configuration
V_IH
V_ICM
V_IL
ates from 50%, every second stage has a shorter time for
settling; thus it operates less accurately, causing degrada-
tion of SNR.
In order to preserve accuracy at high input frequency, it is
important that the clock have low jitter and steep edges.
Rise/fall times should be kept shorter than 2 ns whenever
possible. Overshoot should be minimized. Low jitter is es-
pecially important when converting high-frequency input
signals. Jitter causes the noise floor to rise proportionally
to input signal frequency. Jitter may be caused by crosstalk
on the PCB. It is therefore recommended that the clock
trace on the PCB be made as short as possible.
DIGITAL OUTPUTS
The digital output data appears in offset binary code at
CMOS logic levels. Full-scale negative input results in out-
put code 000...0. Full-scale positive input results in output
code 111...1. Output data are available 6 clock cycles after
the data are sampled. The analog input is sampled one
aperture delay (t_AP) after the high-to-low clock transition.
Output data should be sampled as shown in the timing dia-
gram (figure 5). The OR pin is an out-of-range pin; if the
outputs go either over or under range, OR is set high.
PCB LAYOUT AND DECOUPLING
A well designed PCB is necessary to get good spectral
purity from any high-performance ADC. A multilayer PCB
with a solid ground plane is recommended for optimum
performance. If the system has a split analog and digital
ground plane, it is recommended that all ground pins on
the ADC be connected to the analog ground plane. It is our
experience that this gives the best performance. The
power supply pins should be bypassed using 100 nF
surface mounted capacitors as close to the package pins
as possible. Analog and digital supply pins should be
separately filtered.
Figure 5 – Timing Diagram
N–1
A_IN
Clock
Clock
N
N+1
N+2
N+3
t_AP
t_H
t_D
Data
Data
N–1
Data
N
Data
N+1
Data
N+2
SPT7864
6
11/20/01